PDF IDT74ALVC162835 Data sheet ( Hoja de datos )

Número de pieza	IDT74ALVC162835
Descripción	3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER
Fabricantes	IDT
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No Preview Available ! www.DataSheet4U.com IDT74ALVC162835 3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIALTEMPERATURERANGE IDT74ALVC162835 FEATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V • CMOS power levels (0.4µ W typ. static) • Rail-to-Rail output swing for increased noise margin • Available in TSSOP and TVSOP packages DESCRIPTION: This 18-bit universal bus driver is built using advanced dual metal CMOS technology. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVC162835 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. DRIVE FEATURES: • Balanced Output Drivers: ±12mA • Low switching noise FUNCTIONAL BLOCK DIAGRAM APPLICATIONS: • SDRAM Modules • PC Motherboards • Workstations OE 27 CLK 30 LE 28 A1 54 1D C1 CLK TO 17 OTHER CHANNELS 3 Y1 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE © 2004 Integrated Device Technology, Inc. 1 JANUARY 2004 DSC-4569/2 1 page IDT74ALVC162835 3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIALTEMPERATURERANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VLOAD 6 6 VIH 2.7 2.7 VT 1.5 1.5 VLZ 300 300 VHZ 300 300 CL 50 50 VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF VCC Pulse(1, 2) Generator VIN VOUT D.U.T. 500Ω VLOAD Open GND RT 500Ω CL ALVC Link Test Circuit for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open INPUT OUTPUT 1 OUTPUT 2 tPLH1 tPHL1 tSK (x) tSK (x) VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. SAME PHASE INPUT TRANSITION OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPLH tPHL tPHL Propagation Delay VIH VT 0V VOH VT VOL VIH VT 0V ALVC Link CONTROL INPUT ENABLE tPZL DISABLE tPLZ VIH VT 0V OUTPUT NORMALLY SWITCH CLOSED LOW tPZH OUTPUT NORMALLY HIGH SWITCH OPEN VLOAD/2 VT tPHZ VT 0V VLOAD/2 VOL + VLZ VOL VOH VOH - VHZ 0V ALVC Link Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tSU tH tREM tSU tH Set-up, Hold, and Release Times VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V ALVC Link LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tW Pulse Width VT VT ALVC Link 5 5 Page

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