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PDF W942516CH Data sheet ( Hoja de datos )
| Número de pieza | W942516CH | |
| Descripción | DDR SDRAM | |
| Fabricantes | Winbond | |
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W942516CH
4M × 4 BANKS × 16 BIT DDR SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. KEY PARAMETERS ................................................................................................................... 4
4. PIN CONFIGURATION ............................................................................................................... 5
5. PIN DESCRIPTION..................................................................................................................... 6
6. BLOCK DIAGRAM ...................................................................................................................... 7
7. ELECRICAL CHARACTERISTICS ............................................................................................. 8
7.1 Absolute Maximum Ratings ................................................................................................. 8
7.2 Recommended DC Operating Conditions............................................................................ 8
7.3 Capacitance ......................................................................................................................... 9
7.4 Leakage and Output Buffer Characteristics ......................................................................... 9
7.5 DC Characteristics ............................................................................................................. 10
7.6 AC Characteristics and Operating Condition ..................................................................... 11
7.7 AC Test Conditions ............................................................................................................ 13
8. OPERATION MODE ................................................................................................................. 15
8.1 Simplified Truth Table ........................................................................................................ 15
8.2 Function Truth Table .......................................................................................................... 16
8.3 Function Truth Table for CKE ............................................................................................ 19
8.4 Simplified Stated Diagram.................................................................................................. 20
9. FUNCTIONAL DESCRIPTION.................................................................................................. 21
9.1 Power Up Sequence .......................................................................................................... 21
9.2 Command Function............................................................................................................ 21
9.3 Read Operation.................................................................................................................. 24
9.4 Write Operation .................................................................................................................. 24
9.5 Precharge........................................................................................................................... 24
9.6 Burst Termination............................................................................................................... 25
9.7 Refresh Operation.............................................................................................................. 25
9.8 Power Down Mode............................................................................................................. 25
9.9 Mode Register Operation ................................................................................................... 25
10. TIMING WAVEFORMS ............................................................................................................. 29
10.1 Command Input Timing...................................................................................................... 29
10.2 Timing of the CLK Signals.................................................................................................. 29
Publication Release Date: May 20, 2003
- 1 - Revision A2
1 page  
4. PIN CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC1
VDDQ
LDQS
NC1
VDD
NC1
LDM
WE
CAS
RAS
CS
NC1
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
W942516CH
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
53 NC1
52 VSSQ
51 UDQS
50 NC1
49 VREF
48 VSS
47 UDM
46 CLK
45 CLK
44 CKE
43 NC1
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
Publication Release Date: May 20, 2003
- 5 - Revision A2
5 Page 
W942516CH
7.6 AC Characteristics and Operating Condition
(Notes: 10, 12)
SYMBOL
PARAMETER
tRC Active to Ref/Active Command Period
tRFC Ref to Ref/Active Command Period
tRAS Active to Precharge Command Period
tRCD Active to Read/Write Command Delay Time
tRAP Active to Read with Auto Precharge Enable
tCCD Read/Write(a) to Read/Write(b) Command Period
tRP Precharge to Active Command Period
tRRD Active(a) to Active(b) Command Period
tWR Write Recovery Time
tDAL Auto Precharge Write Recovery + Precharge Time
tCK CLK Cycle Time
CL = 2
CL = 2.5
-7
MIN. MAX.
65
75
45 100000
20
15
1
20
15
15
30
7.5 15
7 15
-75
MIN. MAX.
65
75
45 100000
20
15
1
20
15
15
30
8 15
7.5 15
tAC Data Access Time from CLK, CLK
-0.75 0.75 -0.75 0.75
tDQSCK
tDQSQ
tCH
tCL
tHP
tQH
tRPRE
tRPST
tDS
tDH
tDIPW
tDQSH
tDQSL
tDSS
tDSH
tWPRES
tWPRE
tWPST
tDQSS
tDSSK
tIS
tIH
tIPW
DQS Output Access Time from CLK, CLK
Data Strobe Edge to Output Data Edge Skew
CLk High Level Width
CLK Low Level Width
CLK Half Period (minimum of actual tCH, tCL)
DQ Output Data Hold Time from DQS
DQS Read Preamble Time
DQS Read Postamble Time
DQ and DM Setup Time
DQ and DM Hold Time
DQ and DM Input Pulse Width (for each input)
DQS Input High Pulse Width
DQS Input Low Pulse Width
DQS Falling Edge to CLK Setup Time
DQS Falling Edge Hold Time from CLK
Clock to DQS Write Preamble Set-up Time
DQS Write Preamble Time
DQS Write Postamble Time
Write Command to First DQS Latching Transition
UDQS – LDQS Skew (x 16)
Input Setup Time
Input Hold Time
Control & Address Input Pulse Width (for each input)
-0.75
0.45
0.45
Min.
(tCL,tCH)
THP
-0.75
0.9
0.4
0.5
0.5
1.75
0.35
0.35
0.2
0.2
0
0.25
0.4
0.75
-0.25
0.9
0.9
2.2
0.75
0.5
0.55
0.55
1.1
0.6
1.25
0.25
-0.75
0.45
0.45
Min.
(tCL,tCH)
THP
-0.75
0.9
0.4
0.5
0.5
1.75
0.35
0.35
0.2
0.2
0
0.25
0.4
0.75
-0.25
0.9
0.9
2.2
0.75
0.5
0.55
0.55
1.1
0.6
1.25
0.25
tHZ Data-out High-impedance Time from CLK, CLK
-0.75 0.75 -0.75 0.75
tLZ
tT(SS)
tWTR
tXSNR
tXSRD
tREF
tMRD
Data-out Low-impedance Time from CLK, CLK
SSTL Input Transition
Internal Write to Read Command Delay
Exit Self Refresh to non-Read Command
Exit Self Refresh to Read Command
Refresh Time (8k)
Mode Register Set Cycle Time
-0.75 0.75 -0.75 0.75
0.5 1.5 0.5 1.5
11
75 75
10 10
64 64
15 15
UNITS
nS
tCK
nS
tCK
nS
tCK
nS
tCK
nS
tCK
nS
tCK
ns
tCK
mS
nS
NOTES
16
11
11
11
11
- 11 -
Publication Release Date: May 20, 2003
Revision A2
11 Page | ||
| Páginas | Total 47 Páginas | |
| PDF Descargar | [ Datasheet W942516CH.PDF ] | |
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