PDF K4H2G0638A Data sheet ( Hoja de datos )

Número de pieza	K4H2G0638A
Descripción	Stacked 2Gb A-die SDRAM Specification
Fabricantes	SAMSUNG
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No Preview Available ! www.DataSheet4U.com DDR SDRAM stacked 2Gb A-die (x4) Preliminary DDR SDRAM Stacked 2Gb A-die SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 June. 2005 1 page DDR SDRAM stacked 2Gb A-die (x4) 4.0 Pin Description Preliminary DDR SDRAM st.512Mb x 4 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC A13 VDD NC NC WE CAS RAS CS0 CS1 BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 66 2 65 3 64 4 63 5 62 6 61 7 60 8 59 9 58 10 66Pin TSOPII 57 11 (400mil x 875mil) 56 12 (0.65mm Pin Pitch) 55 13 54 14 Bank Address 15 BA0~BA1 16 53 52 51 17 18 19 Auto Precharge A10 50 49 48 20 47 21 46 22 45 23 44 24 43 25 42 26 41 27 40 28 39 29 38 30 37 31 36 32 35 33 34 stacked 2Gb TSOP-II Package Pinout VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE0 CKE1 A12 A11 A9 A8 A7 A6 A5 A4 VSS Organization st. 512Mx4 Row Address A0~A13 Column Address A0-A9, A11, A12 DM is internally loaded to match DQ and DQS identically. Row & Column address configuration Rev. 0.0 June. 2005 5 Page DDR SDRAM stacked 2Gb A-die (x4) Preliminary DDR SDRAM 14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A IDD1 : Operating current: One bank operation 1. Typical Case: For DDR200,266,333: Vdd = 2.5V, T=25°C; For DDR400: Vdd=2.6V,T=25°C Worst Case : Vdd = 2.7V, T= 10°C 2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 3. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3tCK, tRC = 9tCK, tRAS = 6tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3tCK, tRC = 9tCK, tRAS = 6tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3tCK, tRC = 10tCK, tRAS=7tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3tCK , tRC = 11tCK, tRAS = 8tCK Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing 50% of data changing at every transfer Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT IDD7A : Operating current: Four bank operation 1. Typical Case: For DDR200,266,333: Vdd = 2.5V, T=25°C; For DDR400: Vdd=2.6V,T=25°C Worst Case : Vdd = 2.7V, T= 10°C 2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2tCK, tRCD = 3tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst - A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2tCK, tRCD = 3tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst - B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2tCK, tRCD=3tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst - CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3tCK , tRC = 11tCK, tRAS = 8tCK Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing *50% of data changing at every transfer Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT Rev. 0.0 June. 2005 11 Page

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