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PDF IDT728980 Data sheet ( Hoja de datos )
| Número de pieza | IDT728980 | |
| Descripción | TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256 | |
| Fabricantes | IDT | |
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TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256
IDT728980
.EATURES:
• 256 x 256 channel non-blocking switch
• Serial Telecom Bus Compatible (ST-BUS®)
• 8 RX inputs—32 channels at 64 Kbit/s per serial line
• 8 TX output—32 channels at 64 Kbit/s per serial line
• Three-state serial outputs
• Microprocessor Interface (8-bit data bus)
• 5V Power Supply
• Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 40-pin
Plastic Dip (P-DIP) and 44-pin Plastic Quad Flatpack (PQFP)
• Operating Temperature Range -40°C to +85°C
DESCRIPTION:
The IDT728980 is a ST-BUS® compatible digital switch controlled by a
microprocessor. The IDT728980 can handle as many as 256, 64 Kbit/s input
and output channels. Those 256 channels are divided into 8 serial inputs and
outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form
a multiplexed 2.048 Mb/s stream.
.UNCTIONAL DESCRIPTION
AfunctionalblockdiagramoftheIDT728980deviceisshownonbelow. The
serial ST-BUS® streams operate continuously at 2.048 Mb/s and are arranged
in125µswideframeseachcontaining32,8-bitchannels. Eightinput(RX0-7)
and eight output (TX0-7) serial streams are provided in the IDT728980 device
allowing a complete 256 x 256 channel non-blocking switch matrix to be
constructed. The serial interface clock (C4i) for the device is 4.096 MHz.
The received serial data is internally converted to a parallel format by the on
chip serial-to-parallel converters and stored sequentially in a 256-position Data
Memory. By using an internal counter that is reset by the input 8 KHz frame pulse,
F0i,theincomingserialdatastreamscanbeframedandsequentiallyaddressed.
Data to be output on the serial streams may come from two sources: Data
Memory or Connection Memory. The Connection Memory is 16 bits wide and
.UNCTIONAL BLOCK DIAGRAM
C4i F0i VCC GND
ODE
RX0 Timing
Unit Output MUX
RX1
RX2 Receive
RX3 Serial Data
Data
Streams
Memory
RX4
Transmit
Serial Data
Streams
RX5
Control Register
Connection
RX6 Memory
RX7 Microprocessor Interface
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
DS CS R/W A0/ DTA D0/
A5 D7
CCO
5706 drw01
2001 Integrated Device Technology, Inc.
1
JANUARY 2001
DSC-5706/1
1 page  
IDT728980 Time Slot Interchange
Digital Switch 256 x 256
Commercial Temperature Range
Mode Control
Memory Select
Bits (unused) Bits
76543
Stream Address Bits
210
Bit Name
Description
7 SM (Split Memory)
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except
when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the
operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.
6 PE (Processor Mode) When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE
pin is LOW. When 0, the Connection Memory bits for each channel determine what is output.
5 unused
4-3 MS1-MS0
(Memory Select Bits)
0-0 - Not to be used.
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
2-0 STA2-0
The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the
(Stream Address Bits) subsection of memory made accessible for subsequent operations.
Table 3. Control Register Configuration
No Corresponding Memory
- These bits give 0s if read
7654
Per Channel Control Bits
3210
Bit Name
2 CS (Channel Source)
1 CCO (CCO Bit)
0 OE (Output Enable)
Description
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determine the source of the connection to the location's channel and stream.
This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first.
If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output drive for the location's
channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing
switching matrices to be constructed. A 1 enables the driver and a 0 disables it.
Table 4. Connection Memory High Register
Stream Address Bits
765
4
Channel Address Bits
321
0
Bit Name
7-5(1) Stream Address Bits
4-0(1) Channel Address Bits
Description
The number expressed in binary notation on these 3 bits are the number of the stream for the source of the connection.
Bit 7 is the most significant bit, e.g., If bit 7 is 1, bit 6 is 0 and bit 5 is 0 then the source of the connection is a channel on
RX4.
The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the
connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4
is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with
this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.
Table 5. Connection Memory Low Register
5
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