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PDF HDMP-0552 Data sheet ( Hoja de datos )
| Número de pieza | HDMP-0552 | |
| Descripción | QUAD PORT BYPASS CIRCUIT | |
| Fabricantes | Hewlett-Packard | |
| Logotipo |  |
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Agilent HDMP-0552 Quad Port Bypass
Circuit with CDR and Data Valid
Detection
For Fibre Channel Arbitrated Loops
Data Sheet
Description
The HDMP-0552 is a Quad Port
Bypass Circuit (PBC) with Clock
and Data Recovery (CDR) and
data valid detection capability
included. See Figure 1 for block
diagram. This device minimizes
part count, cost and jitter
accumulation while repeating
incoming signals. Port Bypass
Circuits are used in hard disk
arrays constructed in Fibre
Channel Arbitrated Loop (FC-AL)
configurations. By using Port
Bypass Circuits, hard disks may
be pulled out or swapped while
other disks in the array are
available to the system.
A PBC consists of multiple 2:1
multiplexers daisy chained along
with a CDR. Each port has two
modes of operation: “disk in
loop” and “disk bypassed.” When
the “disk in loop” mode is
selected, the loop goes into and
out of the disk drive at that port.
For example, data goes from the
HDMP-0552’s TO_NODE[n]±
differential output pins to the
Disk Drive Transceiver IC (for
example, an HDMP-263x) Rx±
differential input pins. Data from
the Disk Drive Transceiver IC
Tx± differential output pins goes
to HDMP-0552’s FM_NODE[n]±
differential input pins. Figure 2
and Figure 3 show connection
diagrams for disk drive array
applications. When the “disk
bypassed” mode is selected, the
disk drive is either absent or
nonfunctional, and the loop
bypasses the hard disk.
Multiple HDMP-0552’s may be
cascaded or connected to other
members of the HDMP-04xx
family through the FM_LOOP and
TO_LOOP pins to create loops for
arrays of disk drives greater than
4. See Table 3 to identify which
of the 5 cells (0:4) provides
FM_LOOP, TO_LOOP pins (cell
connected to cable).
Features
• Supports 1.0625/2.125 GBd Fibre
Channel operation
• Quad PBC/CDR in one package
• CDR location determined by
choice of cable input/output
• Amplitude valid detection on
FM_NODE[0] input
• Data valid detection on
FM_NODE[0] input
– Run length violation detection
– Comma detection
– Configurable for both single-
frame and multi-frame
detection
• Speed select pin for 1 or 2 GBd
operation
• Single REFCLK for 1 or 2 GBd
operation
• CDR selectable via external pin
• Enable/disable equalizers on all
inputs
• Enable/disable selected high-
speed output drivers
• High speed LVPECL I/O
• Buffered line logic (BLL) outputs
(no external bias resistors
required)
• 1.1 W typical power at VCC = 3.3 V
• Advanced 0.35 µ BiCMOS
technology
• 64 Pin, 10 mm, low cost plastic
QFP package
Applications
• RAID, JBOD, BTS cabinets
• 1=> 1-4 serial buffer with or
without CDR
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of
this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
1 page  
Table 1 - Pin Definitions for HDMP-0552. Refer to Figure 4 for pin layout
Pin Name
MODE_DV
FSEL
FM_NODE[0]_DV
FM_NODE[0]_AV
TO_NODE[0]+
TO_NODE[0]-
TO_NODE[1]+
TO_NODE[1]-
TO_NODE[2]+
TO_NODE[2]-
TO_NODE[3]+
TO_NODE[3]-
TO_NODE[4]+
TO_NODE[4]-
FM_NODE[0]+
FM_NODE[0]-
FM_NODE[1]+
FM_NODE[1]-
FM_NODE[2]+
FM_NODE[2]-
FM_NODE[3]+
FM_NODE[3]-
FM_NODE[4]+
FM_NODE[4]-
BYPASS[0]-
BYPASS[1]-
BYPASS[2]-
BYPASS[3]-
BYPASS[4]-
CDR_SEL
CDR_RATE
REF_RATE
REFCLK
CPLL1
CPLL0
EQ_SEL
Pin Pin Type
24 I-LVTTL
25 I-LVTTL
23 O-LVTTL
59 O-LVTTL
57 HS_OUT
56
32
31
35
34
44
43
47
46
54 HS_IN
53
29
28
38
37
41
40
51
50
55 I-LVTTL
30
36
42
49
10 I-LVTTL
11 I-SSTL2
12 I-LVTTL
14 I-LVTTL
16 C
17 C
61 I-LVTTL
Pin Description
Data Valid Detect Mode: To allow data valid detection, float MODE_DV
HIGH. To configure chip for "CDR anywhere" capability, connect MODE_DV
to GND through a 1 kW resistor.
Frame Select: To configure single-frame operation of the data valid and
amplitude valid detection circuits, connect FSEL to GND through a 1 kW
resistor. To configure multi-frame (4-frame) operation of the data valid and
amplitude valid detection circuits, float FSEL HIGH.
Data Valid: Indicates valid Fibre Channel Data on the FM_NODE[0]± inputs
when HIGH. Indicates either run length violation error or no comma detected
when LOW.
Amplitude Valid: Indicates acceptable signal amplitude on the
FM_NODE[0]± inputs.
Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable
input.
Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable
output.
Bypass Inputs: For "disk bypassed" mode, connect BYPASS[n]- to GND
through a 1 kW resistor. For "disk in loop" mode, float HIGH.
CDR Select: To configure the chip with the CDR bypassed, connect CDR_SEL
to GND through a 1 kW resistor. To configure the chip with the CDR in the
loop, float CDR_SEL HIGH.
CDR Rate: To configure the chip for 1 GBd operation, connect CDR_RATE to
GND through a 1 kW resistor. To configure the chip for 2 GBd operation,
float CDR_RATE HIGH.
Reference Rate: Float REF_RATE HIGH for a reference rate of 106.25 MHz
and connect REF_RATE to GND via a 1 kW resistor for a reference rate of
53.125 MHz.
Reference Clock: A user-supplied clock reference used for frequency
acquisition in the Clock and Data Recovery (CDR) circuit.
Loop Filter Capacitor: A loop filter capacitor for the internal Clock and Data
Recovery (CDR) circuit must be connected across the CPLL1 and CPLL0 pins.
Recommended value is 0.1 µF.
Equalizer Select: Allows user to select/deselect equalization on any input.
5
5 Page 
Locking Characteristics
Ta = 0°C to Tc = +80°C , VCC = 3.15 V to 3.45 V
Parameter
Units
Bit Sync Time (phase lock)
bits
Frequency Lock at Powerup
µs
Maximum
2500
500
70841B
PATTERN
± DATA
GENERATOR
K28.7
0011111000
CLOCK
2.125 GHz
70311A
CLOCK SOURCE
RANDOM JITTER
2
BIAS
1.4
1/20
VARIABLE
DELAY
106.25 MHz
Figure 8 - Setup for Measurement of Random Jitter
70841B
PATTERN
± DATA
GENERATOR
+K28.5 -K28.5 CLOCK
DETERMINISTIC JITTER
2
BIAS
2.125 GHz
70311A
CLOCK SOURCE
1.4
1/20
VARIABLE
DELAY
106.25 MHz
1/2
Figure 9 - Setup for Measurement of Deterministic Jitter
HDMP-0552
± FM_NODE[0]
REF CLK
BYPASS - [0]
BYPASS - [1]
BYPASS - [2]
BYPASS - [3]
BYPASS - [4]
± TO_NODE[1]
2
TRIGGER
CH 1/2
83480A
DIGITAL
COMMUNICATION
ANALYZER
VCC
HDMP-0552
± FM_NODE[0]
REF CLK
BYPASS - [0]
BYPASS - [1]
BYPASS - [2]
BYPASS - [3]
BYPASS - [4]
± TO_NODE[1]
2
TRIGGER
CH 1/2
83480A
DIGITAL
COMMUNICATION
ANALYZER
VCC
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HDMP-0552.PDF ] | |
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