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HDMP-0480 fiches techniques PDF

Hewlett-Packard - Octal Cell Port Bypass Circuit without Clock and Data Recovery

Numéro de référence HDMP-0480
Description Octal Cell Port Bypass Circuit without Clock and Data Recovery
Fabricant Hewlett-Packard 
Logo Hewlett-Packard 





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HDMP-0480 fiche technique
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Agilent HDMP-0480
Octal Cell Port Bypass Circuit
without Clock and Data Recovery
Data Sheet
Description
The HDMP-0480 is an Octal Cell
Port Bypass Circuit (PBC). This
device minimizes part count, cost
and jitter accumulation. Port
Bypass Circuits are used in hard
disk arrays constructed in Fibre
Channel Arbitrated Loop (FC-AL)
configurations. By using Port
Bypass Circuits, hard disks may
be pulled out or swapped while
other disks in the array are
available to the system.
A Port Bypass Circuit (PBC)
consists of multiple 2:1 multiplex-
ers daisy chained along with a
CDR. Each port has two modes of
operation: “disk in loop” and
“disk by-passed”. When the “disk
in loop” mode is selected, the loop
goes into and out of the disk drive
at that port. For example, data
goes from the HDMP-0480’s
TO_NODE[n]± differential output
pins to the Disk Drive Transceiver
IC’s (e.g. an HDMP-1636A) Rx±
differential input pins. Data from
the Disk Drive Transceiver IC’s
Tx± differential outputs goes to
the HDMP- 0480’s FM_NODE[n]±
differential input pins. When the
“disk bypassed” mode is selected,
the disk drive is either absent or
non-functional and the loop
bypasses the hard disk.
The “disk bypassed” mode is
enabled by pulling the BYPASS[n]-
pin low. Leave BYPASS[n]-
floating to enable the “disk in
loop” mode. HDMP-0480’s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the FM_NODE and
TO_NODE pins to accommodate
any number of hard disks. The
unused cells in this PBC may be
bypassed by using pulldown
resistors on the BYPASS[n]- pins
for these cells.
An HDMP-0480 may also be used
as eight 1:1 buffers. In addition,
an HDMP-0480 may be config-
ured as four 2:1 multiplexers or
as four 1:2 buffers.
Features
• Supports 1.0625 GBd fibre channel
operation
• Supports 1.25 GBd gigabit Ethernet
(GE) operation
• Octal cell PBC in one package
• Valid amplitude detection on
FM_NODE[7] input
• Equalizers on all inputs
• High speed LVPECL I/O
• Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
• 0.76 W typical power at Vcc=3.3V
• 64 Pin, 10 mm, low cost plastic QFP
package
Applications
• RAID, JBOD, BTS cabinets
• Four 2:1 muxes
• Four 1:2 buffers
• 1 = > N gigabit serial buffer
• N = > 1 gigabit serial mux
HDMP-0480
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and
assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).

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