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Número de pieza KVR533D2S8F4
Descripción Memory Module Specifications
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Memory Module Specifications
KVR533D2S8F4/512I
512MB 64M x 72-Bit PC2-4200
CL4 ECC 240-Pin FBDIMM
Description:
This document describes ValueRAM's 512MB (64M x 72-bit) PC2-4200 CL4 SDRAM (Synchronous DRAM) "fully
buffered" ECC "single rank" “Intel Certified” memory module. This module is based on nine 64M x 8-bit 533MHz
DDR2 FBGA components. The module also includes an AMB device (Advanced Memory Buffer). The electrical
and mechanical specifications are as follows:
Feature:
· FBDIMM Module: 240-pin
· JEDEC Standard: R/C A
· Memory Organization: 1 rank of x8 devices
· DDR2 DRAM Interface: SSTL_18
· DDR2 Speed Grade: 533 Mbps
· CAS Latency: 4-4-4
· Module Bandwidth: 4.2 GB/s
· DRAM: VDD = VDDQ = 1.8V
· AMB: VCC = VCCFBD = 1.5V
· EEPROM: VDDSPD = 3.3V (typical)
· Heat Spreader: Full DIMM Heat Spreader (FDHS)
· PCB Height: 30.35mm, double-side
· RoHS Compliant
VALUERAM0502-001.A00
08/28/06
Page 1

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KVR533D2S8F4 pdf
TECHNOLOGY
Architecture:
Advanced Memory Buffer Pin Description:
Pin Name
Pin Description
Count
FB-DIMM Channel Signals
99
SCK
System Clock Input, positive line
1
SCK
System Clock Input, negative line
1
PN[13:0]
Primary Northbound Data, positive lines
14
PN[13:0]
Primary Northbound Data, negative lines
14
PS[9:0]
Primary Southbound Data, positive lines
10
PS[9:0]
Primary Southbound Data, negative lines
10
SN[13:0]
Secondary Northbound Data, positive lines
14
SN[13:0]
Secondary Northbound Data, negative lines
14
SS[9:0]
Secondary Southbound Data, positive lines
10
SS[9:0]
Secondary Southbound Data, negative lines
10
FBDRES
To an external precision calibration resistor connected to Vcc
1
DDR2 Interface Signals
175
DQS[8:0]
Data Strobes, positive lines
9
DQS[8:0]
Data Strobes, negative lines
9
DQS[17:9]/DM[8:0] Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes.
9
DQS[17:9]
Data Strobes (x4 DRAM only), negative lines
9
DQ[63:0]
Data
64
CB[7:0]
Checkbits
8
A[15:0]A, A[15:0]B Addresses. A10 is part of the pre-charge command
32
BA[2:0]A, BA[2:0]B Bank Addresses
6
RASA, RASB
Part of command, with CAS, WE, and CS[1:0].
2
CASA, CASB
Part of command, with RAS, WE, and CS[1:0].
2
WEA, WEB
Part of command, with RAS, CAS, and CS[1:0].
2
ODTA, ODTB On-die Termination Enable
2
CKE[1:0]A, CKE[1:0]B Clock Enable (one per rank)
4
CS[1:0]A, CS[1:0]B Chip Select (one per rank)
4
CLK[3:0]
CLK[1:0] used on 9 and 18 device DIMMs,
put disabled when not in use.
CLK[3:0]
used
on 36 device DIMMs. CLK[3:2] should
be out-
4
CLK[3:0]
Negative lines for CLK[3:0]
4
DDRC_C14
DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18.
1
DDRC_B18
DDR Compensation: Resistor connected to common return pin DDRC_C14
1
DDRC_C18
DDR Compensation: Resistor connected to common return pin DDRC_C14
1
DDRC_B12
DDRC_C12
DDR Compensation: Resistor connected to VSS
DDR Compensation: Resistor connected to VDD
1
1
VALUERAM0502-001.A00
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