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PDF ADSP-21267 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-21267 | |
| Descripción | Preliminary Technical Data | |
| Fabricantes | Analog Devices | |
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Preliminary Technical Data
SHARC® Processor
ADSP-21267
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Code compatible with all other SHARC DSPs
The ADSP-21267 processes high performance audio while
enabling low system costs
Audio decoders and post processor-algorithms support.
Non-volatile memory can be configured to contain a com-
bination of PCM 96 kHz, Dolby Digital, Dolby Digital EX2,
Dolby Pro Logic IIx, DTS 5.1, DTS ES Discrete 6.1, DTS-ES
Matrix 6.1, DTS Neo:6, MPEG2x BC (2 channel) and others.
See www.analog.com/SHARC for a complete list
Single-Instruction Multiple-Data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O —a parallel port, an SPI port, four serial
ports, a digital audio interface (DAI) and JTAG test port
DAI incorporates two precision clock generators (PCG), and
an input data port (IDP) that includes a parallel data acqui-
sition port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)
On-chip memory—1M Bit of on-chip SRAM and a dedicated
3M Bits of on-chip mask-programmable ROM
The ADSP-21267 is available with a 150 MHz core instruction
rate. For complete ordering information, see Ordering
Guide on page 43
Figure 1. FUNCTIONAL BLOCK DIAGRAM
CORE P ROCE SSO R
TIM ER
INSTRUCTION
CACHE
32 X 48-BIT
DAG1
8X4 X3 2
DAG 2
8X 4X32
PROG RAM
SEQ UE NCE R
DUAL PORTED MEMORY
BLOCK 0
S RAM
0.5 MBI T
ROM
1.5 MBIT
ADDR
DATA
DUAL P ORT ED ME MORY
BLOCK 1
S RAM
0.5 MBIT
ROM
1.5 MBI T
ADDR
DATA
PM ADDRE SS BUS
DM ADDRESS BUS
32
32
P ROCE SSI NG
ELEME NT
(PE X)
PRO CE SSI NG
EL EM EN T
(PEY )
PX REGIS TER
64 P M DATA BUS
64 DM DATA BUS
DMA CONTROLLER
2 2 C HA N N ELS
4
S PI PORT (1)
JTAG TES T & EMULATIO N
6
S
SERIAL P ORTS (6)
20 SIG NAL
ROUTING
UNIT
INPUT
DATA P ORTS (8)
P ARALLEL DATA
ACQUIS ITION PO RT
PRE CI SION CLOCK
G ENERATO RS (2)
3
TI ME RS (3)
IO D IOA
(32) (18)
GPIO FLAG S/
IRQ /TIMEXP
4
I OP
REGIS TERS
(MEMO RY MAP PED)
CONTROL,
STATUS, &
DAT A BUFFERS
A D D RE SS/
D A TA B U S/ GP IO
CON TR OL/G PIO
PARALLEL
PORT
16
3
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
1 page  
PRELIMINARY TECHNICAL DATA
ADSP-21267
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21267 contain
sufficient registers to allow the creation of up to 32 circular buff-
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wrap-around, reduce
overhead, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21267 can conditionally execute a multiply, an add, and a sub-
tract in both processing elements while branching and fetching
up to four 32-bit values from memory; all in a single instruction.
ADSP-21267 MEMORY AND I/O INTERFACE
FEATURES
The ADSP-21267 adds the following architectural features to
the SIMD SHARC family core:
Dual-Ported On-Chip Memory
The ADSP-21267 contains one megabit of internal SRAM and
three megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see ADSP-21267 Memory Map on page 6). Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dual-
ported memory, in combination with three separate on-chip
buses, allow two data transfers from the core and one from the
I/O processor, in a single cycle.
On the ADSP-21267, the SRAM can be configured as a maxi-
mum of 32K words of 32-bit data, 64K words of 16-bit data, 21K
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to one megabit. All of the memory can
be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively dou-
bles the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one dedicated to each
memory block assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
DMA Controller
The ADSP-21267’s on-chip DMA controller allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions. DMA transfers
can occur between the ADSP-21267’s internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
port, the IDP (input data port/parallel data acquisition port) or
the parallel port. Eighteen channels of DMA are available on the
ADSP-21267 — one for the SPI interface, eight via the serial
ports, eight via the Input Data Port and one via the processor’s
parallel port. Programs can be downloaded to the ADSP-21267
using DMA transfers. Other DMA features include interrupt
generation upon completion of DMA transfers, and DMA
chaining for automatic linked DMA transfers.
Digital Audio Interface (DAI)
The Digital Audio Interface (DAI) provides the ability to con-
nect various peripherals to any of the DSPs DAI pins
(DAI_P[20:1]).
Programs make these connections using the Signal Routing
Unit (SRU, shown in the block diagram on page 1).
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with non-
configurable signal paths.
The DAI also includes 4 serial ports, 2 precision clock genera-
tors (PCG), an input data port (IDP), 6 flag outputs and 6 flag
inputs, and 3 timers. The IDP provides an additional input path
to the ADSP-21267 core, configurable as either eight channels
of I2S or serial data or as seven channels plus a single 20-bit wide
synchronous parallel data acquisition port Each data channel
has its own DMA channel that is independent from the ADSP-
21267's serial ports.
For complete information on using the DAI, see the ADSP-
2126x SHARC DSP Peripherals Manual.
Serial Ports
The ADSP-21267 features four full duplex synchronous serial
ports that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices such as the AD183x
family of audio codecs, ADCs, and DACs. The serial ports are
made up of two data lines, a clock and frame sync. The data
lines can be programmed to either transmit or receive and each
data line has its own dedicated DMA channel.
Serial ports are enabled via 8 programmable and simultaneous
receive or transmit pins that support up to 16 transmit or 16
receive channels of audio data when all four SPORTS are
enabled, or four full duplex TDM streams of 128 channels per
frame.
The serial ports operate at up to one-quarter of the DSP core
clock rate, providing each with a maximum data rate of 37.5
Mbits/s for a 150 MHz core. Serial port data can be automati-
cally transferred to and from on-chip memory via a dedicated
DMA. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. One SPORT pro-
vides two transmit signals while the other SPORT provides the
two receive signals. The frame sync and clock are shared.
Serial ports operate in four modes:
• Standard DSP serial mode
• Multichannel (TDM) mode
Rev. PrA | Page 5 of 44 | January 2004
5 Page 
PRELIMINARY TECHNICAL DATA
ADSP-21267
Table 2. Pin Descriptions (Continued)
Pin
DAI_P20-1
SPICLK
SPIDS
MOSI
MISO
BOOTCFG1-0
Type
I/O/T
I/O
I
I/O (O/D)
I/O (O/D)
I
State During &
After Reset
Function
Three-state with Digital Audio Interface Pins. These pins provide the physical interface to the SRU.
programmable pull- The SRU configuration registers define the combination of on-chip peripheral
up inputs or outputs connected to the pin and to the pin’s output enable. The config-
uration registers of these peripherals then determines the exact behavior of the pin.
Any input or output signal present in the SRU may be routed to any of these pins.
The SRU provides the connection from the Serial ports, Input data port, precision
clock generators and timers to the DAI_P20-1 pins These pins have internal 22.5 KΩ
pull-up resistors which are enabled on reset. These pull-ups can be disabled in the
DAI_PIN_PULLUP register.
Three-state with
pull-up enabled
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of
baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that
is active during data transfers, only for the length of the transferred word. Slave
devices ignore the serial clock if the slave select input is driven inactive (HIGH).
SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines.
The data is always shifted out on one clock edge and sampled on the opposite edge
of the clock. Clock polarity and clock phase relative to data are programmable into
the SPICTL control register and define the transfer format. SPICLK has a 22.5 KΩ
internal pull-up resistor.
Input only
Serial Peripheral Interface Slave Device Select. An active low signal used to select
the DSP as an SPI slave device. This input signal behaves like a chip select, and is
provided by the master device for the slave devices. In multi-master mode the DSPs
SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that
an error has occurred, as some other device is also trying to be the master device.
If asserted low when the device is in master mode, it is considered a multi-master
error. For a single-master, multiple-slave configuration where flag pins are used, this
pin must be tied or pulled high to VDDEXT on the master device. For ADSP-21267 to
ADSP-21267 SPI interaction, any of the master ADSP-21267's flag pins can be used
to drive the SPIDS signal on the ADSP-21267 SPI slave device.
Three-state with
pull-up enabled
SPI Master Out Slave In. If the ADSP-21267 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21267
is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving
input data. In an ADSP-21267 SPI interconnection, the data is shifted out from the
MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s).
MOSI has a 22.5 KΩ internal pull-up resistor.
Three-state with
pull-up enabled
SPI Master In Slave Out. If the ADSP-21267 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21267 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, trans-
mitting output data. In an ADSP-21267 SPI interconnection, the data is shifted out
from the MISO output pin of the slave and shifted into the MISO input pin of the
master. MISO has a 22.5KΩ internal pull-up resistor. MISO can be configured as O/D
by setting the OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable
broadcast transmission to multiple SPI-slaves, the DSP's MISO pin may be disabled
by setting (=1) bit 5 (DMISO) of the SPICTL register.
Input only
Boot Configuration Select. Selects the boot mode for the DSP. The BOOTCFG pins
must be valid before reset is asserted. See Table 4 on page 13 for a description of
the boot modes.
Rev. PrA | Page 11 of 44 | January 2004
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADSP-21267.PDF ] | |
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