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PDF UPD8873 Data sheet ( Hoja de datos )

Número de pieza UPD8873
Descripción CCD LINEAR IMAGE SENSOR
Fabricantes NEC 
Logotipo NEC Logotipo



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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD8873
(5400 × 5400) PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The µ PD8873 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The µ PD8873 has 3 rows of (5400 + 5400) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
1200 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
Valid photocell : (5400 + 5400) staggered pixels × 3
Photocell pitch : 5.25 µ m
Line spacing : 63 µ m (12 lines) Red line - Green line, Green line - Blue line
Color filter
10.5 µ m (2 lines) Odd line - Even line (for each color)
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
Resolution
: 48 dot/mm A4 (210 × 297 mm) size (shorter side)
1200 dpi US letter (8.5” × 11”) size (shorter side)
Drive clock level : CMOS output under 5 V operation
Data rate
: 12.5 MHz Max.
Power supply : +12 V
On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
µ PD8873CY
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16614EJ2V0DS00 (2nd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
2003

1 page




UPD8873 pdf
µ PD8873
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp clock voltage
dpi select signal voltage
Transfer gate clock voltage
Operating ambient temperature Note
Storage temperature
Symbol
VOD
Vφ 1, Vφ 2
Vφ R
Vφ CLB
Vφ SEL
Vφ TG1 to Vφ TG3
TA
Tstg
Note Use at the condition without dew condensation.
Ratings
0.3 to +15
0.3 to +8
0.3 to +8
0.3 to +8
0.3 to +8
0.3 to +8
0 to +60
40 to +70
Unit
V
V
V
V
V
V
°C
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
dpi select signal high level
dpi select signal low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
Clock pulse frequency
Symbol
VOD
Vφ 1H, Vφ 2H
Vφ 1L, Vφ 2L
Vφ RH
Vφ RL
Vφ CLBH
Vφ CLBL
Vφ SELH
Vφ SELL
Vφ TG1H to Vφ TG3H
Vφ TG1L to Vφ TG3L
fφ R
fφ 1, fφ 2
Min.
11.4
4.75
0
4.75
0
4.75
0
4.75
0
4.75
0
Typ.
12.0
5.0
0
5.0
0
5.0
0
5.0
0
Vφ 1H Note
0
2.0
2.0
Max.
12.6
5.5
0.15
5.5
0.15
5.5
0.15
5.5
0.15
Vφ 1H Note
0.15
12.5
12.5
Unit
V
V
V
V
V
V
V
V
V
V
V
MHz
MHz
Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H),
Image lag can increase.
Data Sheet S16614EJ2V0DS
5

5 Page





UPD8873 arduino
TIMING CHART 1-4 (600 dpi, line clamp mode, for each color)
φ TG1 to φ TG3
φ1
φ2
φR
φ CLB
(φ TG1 to φ TG3)
Note
φ SEL “L”
VOUT1 to VOUT3
Optical black
(24 pixels)
Valid photocell
(5400 pixels)
Invalid photocell
(2 pixels)
Invalid photocell
(2 pixels)
Note Set the φ R and φ CLB to low level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
Note

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