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PDF IM29LV001T Data sheet ( Hoja de datos )
| Número de pieza | IM29LV001T | |
| Descripción | Flash Memory | |
| Fabricantes | ETC | |
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Preliminary Specification
IMT
IM29LV001T and IM29LV001B
1 M Bit (128K x 8) 3.3V-Only Flash Memory
Features:
• 0.40 µm, triple-poly double-metal CMOS
process
• Single power supply operation
3.3V ± 10% for both read and write
• High endurance
> 10,000 program/erase cycles
• Fast read access time
70 and 90 ns
• Single page erasability for optimal data
alterability
Page size: 512 bytes
• Hardwired data protection
Inhibits program and erase operations of
the top (IM29LV001T) or bottom
(IM29LV001B) 32 pages of the array for
false write and virus prevention.
• Flexible boot block configurability
• Fast program and erase operations:
Byte program : < 35 µsec typical
General Descriptions
The IM29LV001T/B is a 1 Mega-bit, 5V-only
page erasable flash memory organized as
128K X 8 bits.It is manufactured with IMT’s
proprietary double metal, 0.40 µm CMOS
flash technology. High performance cell
design and advanced process technology
attain better reliability, manufacturability,
circuit performance and future scaleability
than other alternative approaches. Fast,
self-timed program/erase operations are
made possible with an innovative cell and
array architecture which is free from the
over-erase problem of the traditional
stacked-gate structures.
Single page (512 bytes) data alterability
ensures optimum flexibility and efficiency in
program codes, parameters and data
storage. It also allows backward compatibility
Page erase : < 7 msec typical
Chip erase : < 2 sec typical
• Self-timed program/erase operations
with end-of-cycle detection
Data# Polling and Toggle Bit
• Inadvertent write protection
Glitch filtering for WE# and CE#
Low Vcc (< 2.2 V ) write inhibit
Hardwired data protection
• Low Icc for power conservation
Read: 6 ma typical
Write: 10 ma typical
Stand-by: 10 µA typical
• Compatible with JEDEC byte wide pin-
out and single-supply flash command
standards
• Package types:
32-pin PLCC, TSOP and PDIP
Others available upon request
to other large-erase-block based flash
products for direct replacement.
The IM29LV001T/B is designed with
interface features for direct in-system
programming and erase operations. Vendor
re-programmable, hardwired data protection
is provided for absolute prevention in
inadvertent data alteration and virus
infection.
The IM29LV001 conforms to the JEDEC byte
wide memory pin-out and single supply flash
command standards.
Designed, manufactured and tested for
extended endurance applications, the
IM29LV001 is specified for more than 104
cycling endurance and greater than 10 years
of data retention.
This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27
Integrated Memory Technologies, Inc.
2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696
1 page  
Preliminary Specification
IMT
Command
First Cycle Second Cycle Third Cycle
Add Data Add Data Add Data
Read Hardwired 5555H AAH 2AAAH 55H 5555H 90H
Protection Status Bit
Fourth Cycle
Add
A16 - A2 A1 A0
Data/Status
Don’t Care 1 0 Protected: D0 = 1, D7-1=Don’t Care
Unprotected: D0 = 0, D7-1=Don’t Care
Table 3 Hardwired Protection Status Bit Read Command
protection mode can also be verified by
software means. See Table 3 for the
command code to access the status bit of
the top and bottom sector. The hardwired
data protection mode can not be disabled by
software means, however.
Noise/Glitch Protection: A WE# or CE# noise
glitch of less than 5 ns will not initiate a
program or erase cycle.
VCC Power Up/Down Detection: The program
or erase operation is inhibited when VCC is
less than 3.5V.
Write Inhibit Mode: The program or erase
operation is inhibited if any one of the
following conditions is enforced: OE# low,
CE# high, or WE# high. This prevents
inadvertent data alterations during power-up
or power-down period.
Product Identification
The product identification mode identifies the
device as the IM29LV001T/B and the
manufacturer as IMT. This mode may be
accessed by hardware or software
operations. They are typically used by a
Flash Memory programmer to identify the
IMT IM29LV001T/B device and apply the
correct algorithm to program the data. See
Table 1 for hardware operation or Table 2
for software operation codes. The
manufacturer ID for IMT is consisted of two
bytes. The first byte is 7F which is located at
A0=0 and A1=0. The second byte is 1F,
located at A0=1 and A1=1. The device ID is
A1, located at A1=0 and A0=1. See Table 4
Byte 1
Byte 2
Address
Data
Address Data
ID Type A16-2 A1 A0
A16-2 A1 A0
Manufacturer ID X 0 0
7FH
X 1 1 1FH
Device ID
X 0 1 A5H/A6HNote Not Applicable
Note: A5H for IM29LV001T and A6H for IM29LV001B
Table 4
Product Identification Table
for manufacturer and device ID designations.
Termination of Product Identification
Mode
To return to the standard read mode, the
Software Product Identification mode must
be terminated. It is accomplished by issuing
the Reset/Read operation, which returns the
device to the read operation. See Table 2 for
the Reset/Read command codes.
This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27
Integrated Memory Technologies, Inc.
2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696
5 Page 
Preliminary Specification
IMT
ADDRESS
WE
CE
OE
DQ7
t CEP
t OEH
X
t OEP
X
t WHWH1,2,or 3
X
Fig. 7 Data Polling Timing Diagram
t OES
X
ADDRESS
WE
CE
OE
DQ6
tOEH
X
t CEP
t OEP
t WHWH1,2,or 3
Fig. 8 Toggle Bit Timing Diagram
tOES
This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27
Integrated Memory Technologies, Inc.
2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696
11 Page | ||
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| PDF Descargar | [ Datasheet IM29LV001T.PDF ] | |
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