S71NS128N Datasheet PDF - SPANSION
| Part Number | S71NS128N | |
| Description | Burst-mode Multiplexed Flash Memory | |
| Manufacturers | SPANSION | |
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S71NS-N MCP Products
MirrorBitTM 1.8 Volt-only Simultaneous Read/Write,
Burst-mode Multiplexed Flash Memory:
256 Mb (16 Mb x 16-bit), 128 Mb (8 Mb x 16-bit) and
64 Mb (4 Mb x 16-bit) with Burst-mode Multiplexed
pSRAM: 64 Mb (4 Mb x 16-bit), 32 Mb (2 Mb x 16-bit)
and 16 Mb (1 Mb x 16-bit)
Data Sheet
ADVANCE
INFORMATION
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion Inc. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion Inc.
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S71NS-N_00 Revision A Amendment 3 Issue Date October 10, 2006
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Advance Information
2 Input/Output Descriptions
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
AMAX – A16
ADQ15 – ADQ0
OE#
WE#
VSS
NC
RDY
CLK
AVD#
F-RST#
F-WP#
F-ACC
R-CE1#
F-CE#
R-CRE
F-VCC
R-VCC
R-UB#
R-LB#
DNU
Description
Address inputs
Multiplexed Address/Data
Output Enable input. Asynchronous relative to CLK for the Burst mode.
Write Enable input.
Ground
No Connect; not connected internally
Ready output. Indicates the status of the Burst read. The WAIT# pin of the
pSRAM is tied to RDY.
Clock input. In burst mode, after the initial word is output, subsequent
active edges of CLK increment the internal address counter. Should be at
VIL or VIH while in asynchronous mode
Address Valid input. Indicates to device that the valid address is present
on the address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode,
causes starting address to be latched.
High = device ignores address inputs
Hardware reset input. Low = device resets and returns to reading array
data
Hardware write protect input. At VIL, disables program and erase functions
in the four outermost sectors. Should be at VIH for all other conditions.
Accelerated input. At VHH, accelerates programming; automatically places
device in unlock bypass mode. At VIL, disables all program and erase
functions. Should be at VIH for all other conditions.
Chip-enable input for pSRAM.
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
Control Register Enable (pSRAM).
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM)
Do Not Use
Flash
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RAM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
October 10, 2006 S71NS-N_00_A3
S71NS-N MCP Products
3
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for S71NS128N electronic component. |
| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ S71NS128N.PDF Datasheet ] | |
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