PDF HY5DV281622DT Data sheet ( Hoja de datos )

Número de pieza	HY5DV281622DT
Descripción	128M(8Mx16) GDDR SDRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! www.DataSheet4U.com HY5DV281622DT 128M(8Mx16) GDDR SDRAM HY5DV281622DT This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5 / Aug. 2003 1 page PIN DESCRIPTION PIN TYPE CK, /CK Input CKE Input /CS BA0, BA1 Input Input A0 ~ A11 Input /RAS, /CAS, /WE Input LDM, UDM Input LDQS, UDQS DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ VREF NC I/O I/O Supply Supply Supply NC HY5DV281622DT DESCRIPTION Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied. Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com- mands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE- CHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. Input Data Mask: DM(LDM,UDM) is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corre- sponds to the data on DQ8-Q15. Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. Rev. 0.5 / Aug. 2003 5 5 Page OPERATION COMMAND TRUTH TABLE - III HY5DV281622DT Current State ROW ACTIVATING WRITE RECOVERING WRITE RECOVERING WITH AUTOPRE- CHARGE REFRESHING /CS /RAS /CAS /WE HXXX L HHH L HHL LHLH LHLL L L HH L LHL L L LH LLLL HXXX L HHH L HHL LHLH LHLL L L HH L LHL L L LH LLLL HXXX L HHH L HHL LHLH LHLL L L HH L LHL L L LH LLLL HXXX L HHH L HHL LHLH Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP Action NOP - Enter ROW ACT after tRCD NOP - Enter ROW ACT after tRCD ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,9,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP - Enter ROW ACT after tWR NOP - Enter ROW ACT after tWR ILLEGAL4 ILLEGAL ILLEGAL ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter precharge after tDPL NOP - Enter precharge after tDPL ILLEGAL4 ILLEGAL4,8,10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tRC NOP - Enter IDLE after tRC ILLEGAL11 ILLEGAL11 Rev. 0.5 / Aug. 2003 11 11 Page

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