PDF HY5756820C Data sheet ( Hoja de datos )

Número de pieza	HY5756820C
Descripción	4 Banks x 8M x 8Bit Synchronous DRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! www.DataSheet4U.com HY57V56820C(L)T 4 Banks x 8M x 8Bit Synchronous DRAM DESCRIPTION The HY57V56820C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. The HY57V56820C is organized as 4banks of 8,388,608x8. The HY57V56820C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro- nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • Single 3.3±0.3V power supply • All device pins are compatible with LVTTL interface • JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch • All inputs and outputs referenced to positive edge of system clock • Data mask function by DQM • Internal four banks operation • Auto refresh and self refresh • 8192 refresh cycles / 64ms • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. HY57V56820CT-6 HY57V56820CT-K HY57V56820CT-H HY57V56820CT-8 HY57V56820CT-P HY57V56820CT-S HY57V56820CLT-6 HY57V56820CLT-K HY57V56820CLT-H HY57V56820CLT-8 HY57V56820CLT-P HY57V56820CLT-S Clock Frequency 166MHz 133MHz 133MHz 125MHz 100MHz 100MHz 166MHz 133MHz 133MHz 125MHz 100MHz 100MHz Power Normal Low power Organization 4Banks x 8Mbits x8 Interface Package LVTTL 400mil 54pin TSOP II This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / July 2003 1 1 page HY57V56820C(L)T CAPACITANCE (TA=25°C, f=1MHz) Parameter Pin Symbol Input capacitance Data input / output capacitance CLK A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM DQ0 ~ DQ15 CI1 CI2 CI/O -6/K/H Min Max 2.5 3.5 2.5 3.8 4.0 6.5 OUTPUT LOAD CIRCUIT -8/P/S Min Max 2.5 4.0 2.5 5.0 4.0 6.5 Unit pF pF pF Output Vtt=1.4V RT=250 Ω Output 50pF 50pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V) Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol ILI ILO VOH VOL Min. -1 -1 2.4 - Note : 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6V Max 1 1 - 0.4 Unit uA uA V V Note 1 2 IOH = -4mA IOL = +4mA Rev. 0.4 / July 2003 5 5 Page COMMAND TRUTH TABLE HY57V56820C(L)T Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/ AP BA Note Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-Single-WRITE Self Refresh1 Entry Exit H H H H H H H H H H H L Precharge power down Entry Exit H L Clock Suspend Entry Exit H L X LLLLX OP code HXXX XX L HHH X X L LHHX RA V L X L H L H X CA V H L X L H L L X CA V H HX X LLHLX X LV X LHHL X X X VX H L L LHX X X L L LHX A9 Pin High (Other Pins OP code) L L L LHX HXXX HX L HHH X HXXX LX L HHH HXXX HX L HHH X HXXX LX LVVV X H XX Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation Rev. 0.4 / July 2003 11 11 Page

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