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PDF NCP5008 Data sheet ( Hoja de datos )
| Número de pieza | NCP5008 | |
| Descripción | (NCP5008 / NCP5009) Backlight LED Boost Driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP5008, NCP5009
Backlight LED Boost Driver
The NCP5008/NCP5009 is a high efficiency boost converter
operating in current loop control mode to drive Light Emitting
Diode. The current mode regulation allows a uniform brightness of
the LEDs.
Features
• 2.7 to 6.0 V Input Voltage Range
• Output Voltage from Vbat to 15 V
• 3.0 mA Quiescent Supply Current
• Automatically LEDs Current Matching
• No External Sense Resistor
• Includes Dimming Function
• Programmable or Automatic Current Output Mode
• LOCAL or REMOTE Control Facility
• Photo Transistor Sense Feedback Input
• Inductor Based Converter brings High Efficiency
• Low Noise DC/DC Converter
• All Pins are Fully ESD Protected
Typical Applications
• LED Display Back Light Control
• High Efficiency Step Up Converter
R1
30 k
GND
U1
1 Iref
2
PHOTO
Vbat
C1
Vbat 10
9
L1
10 mF/6.3 V
GND
Q1
NPN−PHOTO
Vbat
GND
Vcc
4
3
5
VBIAS
CS
CLK
NCP5009
D1 D2
8
L2
7
GND
6
LOCAL
D3 D4
L1
22 mH
D5 MBR0520
GND
http://onsemi.com
MARKING
DIAGRAM
10
1
Micro 10
DM SUFFIX
CASE 846B
5Tx
AYW
x = Device Number 8 or 9
A = Assembly Location
Y = Year
W = Work Week
PIN CONNECTIONS
Iref
NC
CS
VBIAS
CLOCK
1
2
3
4
5
10 Vbat
9 L1
8 L2 Iout
7 GND
6 LOCAL
NCP5008
Iref
Photo
CS
VBIAS
CLOCK
1
2
3
4
5
10 Vbat
9 L1
8 L2 Iout
7 GND
6 LOCAL
NCP5009
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
LED LED LED LED
GND
C2
GND
2.2 mF/16 V
Figure 1. Typical Battery Powered LED Boost Driver
© Semiconductor Components Industries, LLC, 2003
August, 2003 − Rev. 4
1
Publication Order Number:
NCP5008/D
1 page  
NCP5008, NCP5009
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply
Output Power Supply Voltage Compliance
Digital Input Voltage
Digital Input Current
Vbat, VBIAS
VL2
CLK, CS
7.0
16
−0.3 tV tVbat + 3.0 V
1.0
V
V
V
mA
Human Body Model: R = 1500 W, C = 100 pF
ESD
"2.0
kV
Machine Model
ESD
"200
V
Micro 10 Package
Power Dissipation @ TA = +85°C
Thermal Resistance Junction−to−Air
PD
RThja
200 mW
200 °C/W
Operating Ambient Temperature Range
TA
−25 to +85
°C
Operating Junction Temperature Range
TJ
−25 to +125
°C
Maximum Junction Temperature
TJmax
+150
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum−rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
POWER SUPPLY SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)
Rating
Pin Symbol
Power Supply
Power Supply Threshold Start Up Voltage
Output Load Voltage Compliance
Pulsed Current Regulation Range
Continuous DC Current in the Load
Output Pulsed Current Tolerance @ Vbat = 3.6 V, L1 = 22 mH/0.71 W,
Rref "1%, ILED = 20 mA (Note 1)
10 Vbat
10 VbatThr
8 Vout
8 Iout
8 Iout
8 Iout
Output Leakage @ LOCAL = 0, CS = H, Vout = 15 V, Vbat = 6.0 V
Standby Current @ Iout = 0 mA, CS = H, CLK = H, Vbat = VBIAS = 3.6 V
Standby Current @ Iout = 0 mA, CS = H, CLK = H, Vbat = VBIAS = 6.0 V
Operating Current @ Vbat = VBIAS = 3.6 V, Iref = 30 mA, CLK = H, CS = L,
LOCAL = Open
8
10
10
10
Iout
Istdb
Istdb
Iope
Boost Internal Oscillator Clock @ L1 = 22 mH, Vbat = VBIAS = 3.6 V,
Iout = 20 mA (Vout = 14 V)
− Fosc
1. The tolerance refers to the 20 mA to 70 mA current range.
Min Typ Max Unit
2.7 − 6.0 V
−
2.3 2.7
V
− − 15.0 V
0 − 400 mA
− − 75 mA
−
"5.0
−
%
− − 500 nA
− 3.0 − mA
− − 10 mA
− 600 −
mA
− 300 − kHz
http://onsemi.com
5
5 Page 
NCP5008, NCP5009
Remote Control Programming Sequence
tCSsetup
CS
CLEAR
CLK
Qdata
tclear
B1
B2
B3
B4
B5
B6
B7
Iout ref
Last Latched Bit
Output Current Programmed Register
Internal Latch Data and Reset
Iout
Ioutdly
Figure 19. Programming Sequence
Upon CS transition from High to Low, the internal
sequence will take place:
− Qdata is internally set to high level.
− Upon positive going transition of the next CLK signal,
the Qdata is shifted to the next Bn stage.
− Clear the Qdata flip−flop upon the positive going of
the SetReg[B1] transient.
The sequence keeps going until CS = High.
When the CS line returns to a High state, the
programming output current flip−flop is set according to
the previous state of the shift register and SetReg B[1−7] is
cleared afterward.
Depending upon the CS width, for a given CLK period,
the last SetReg bit will be latched and the output current
will be adjusted accordingly. If the number of CLK pulses
is higher than 7, the Qdata is lost and the SetReg register
bits B[1−7] are in the Low state, yielding a zero output
current.
The internal shift register can be clear by sending more
than 7 pulses to the CLK pin when the pin CS is low. If the
internal shift register is clear upon the CS transition from
Low to High, the device will be placed or maintained in the
shut down mode.
When the register content is higher than zero, the DC/DC
is activated and a 100 ms delay (typical) is necessary to
stabilize the output current to the programmed value.
http://onsemi.com
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet NCP5008.PDF ] | |
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