NTB35N15 Datasheet PDF - ON Semiconductor
| Part Number | NTB35N15 | |
| Description | Power MOSFET ( Transistor ) | |
| Manufacturers | ON Semiconductor | |
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NTB35N15
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Power MOSFET
37 Amps, 150 Volts
N–Channel Enhancement–Mode D2PAK
Features
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Avalanche Energy Specified
• IDSS and RDS(on) Specified at Elevated Temperature
• Mounting Information Provided for the D2PAK Package
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage
Drain–to–Source Voltage (RGS = 1.0 MW)
Gate–to–Source Voltage
– Continuous
– Non–Repetitive (tpv10 ms)
Drain Current
– Continuous @ TA = 25°C
– Continuous @ TA = 100°C
– Pulsed (Note 2)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Operating and Storage Temperature Range
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
TJ, Tstg
150 Vdc
150 Vdc
"20
"40
Vdc
Adc
37
23
111
178 Watts
1.43 W/°C
2.0 Watts
–55 to °C
+150
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
IL(pk) = 21.6 A, L = 3.0 mH, RG = 25 W)
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient
– Junction–to–Ambient (Note 1)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
EAS 700 mJ
RqJC
RqJA
RqJA
TL
°C/W
0.7
62.5
50
260 °C
1. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu. Area 0.412 in2).
2. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
http://onsemi.com
37 AMPERES
150 VOLTS
50 mW @ VGS = 10 V
N–Channel
D
G
S
MARKING DIAGRAM
& PIN ASSIGNMENT
4
12
3
D2PAK
CASE 418B
STYLE 2
4
Drain
NTB35N15
LLYWW
1
Gate
2
Drain
3
Source
NTB35N15 = Device Code
LL = Location Code
Y = Year
WW = Work Week
ORDERING INFORMATION
Device
NTB35N15
NTB35N15T4
Package
D2PAK
D2PAK
Shipping
50 Units/Rail
800/Tape & Reel
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2002
May, 2002 – Rev. 2
1
Publication Order Number:
NTB35N15/D
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NTB35N15
12
10
VDS
8
6 Q1
QT
Q2
120
100
VGS 80
60
1000
VDD = 75 V
ID = 37 A
VGS = 10 V
100
td(off)
tf
tr
4 40
2 ID = 37 A 20
TJ = 25°C
00
0 10 20 30 40 50 60 70
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
td(on)
10
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
40
35
VGS = 0 V
TJ = 25°C
30
25
20
15
10
5
0
0.2 0.3
0.4 0.5 0.6 0.7
0.8 0.9
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance –
General Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) – TC)/(RqJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
http://onsemi.com
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