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PDF TC5117400BST Data sheet ( Hoja de datos )
| Número de pieza | TC5117400BST | |
| Descripción | DYNAMIC RAM | |
| Fabricantes | Toshiba Semiconductor | |
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TOSHIBA
TC5117400BSJ/BST-60/70
4,194,304 WORD X 4 BIT DYNAMIC RAM
PRELIMINARY
Description
The TC5117400BSJ/BST is the new generation dynamic RAM organized 4,194,304 word by 4 bits. The TC5117400BSJ/BST uti-
lizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins,
both internally and to the system user. Multiplexed address inputs permit the TC5117400BSJ/BST to be packaged in a 26/24 pin
plastic SOJ (300mil), and 26/24 pin plastic TSOP (300mil). The package size provides high system bit densities and is compatible
with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V± 10%
tolerance, direct interfacing capability with high performance logic families such as Schottky TTL.
Features
• 4,194,304 word by 4 bit organization
• Fast access time and cycle time
• Single power supply of 5V± 10% with a built-in
VBB generator
• Low Power
- 605mW MAX. Operating
- (TC5117400BSJ/BST-60)
- 523mW MAX. Operating
- (TC5117400BSJ/BST-70)
- 5.5mW MAX. Standby
• Outputs unlatched at cycle end allows two-
dimensional chip selection
• Common I/O capability using “EARLY WRITE”
operation
• Read-Modify-Write, CAS before RAS refresh,
RAS-only refresh, Hidden refresh, Fast Page
Mode and Test Mode capability
• All inputs and outputs TTL compatible
• 2048 refresh cycles/32ms
• Package TC5117400BSJ: SOJ26-P-300C
TC5117400BST: TSOP26-P-300D
Key Parameters
ITEM
tRAC
tAA
RAS Access Time
Column Address
Access Time
tCAC
tRC
tPC
CAS Access Time
Cycle Time
Fast Page Mode
Cycle Time
TC5117400BSJ/BST
-60
60ns
-70
70ns
30ns
35ns
15ns
110ns
20ns
130ns
40ns
45ns
1. This technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to export. Any export or re-export, directly or indi-
rectly, in contravention of the U.S. Export Administration Regulations is strictly prohibited.
2. LIFE SUPPORT POLICY
Toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate officer of Toshiba America, Inc. Life support sys-
tems are either systems intended for surgical implant in the body or systems which sustain life.
A critical component in any component of a life support system whose failure to perform may cause a malfunction of the life support system, or may affect its safety or effectiveness.
3. The information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. All information in this data book
is subject to change without prior notice. Furthermore, Toshiba cannot assume responsibility for the use of any license under the patent rights of Toshiba or any third parties.
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
1
1 page  
DR16040794
Standard DRAM
TC5117400BSJ/BST-60/70
Electrical Characteristics and Recommended AC Operating Conditions (VCC = 5V ± 10%, Ta = 0~70°C) (Notes 6,7,8)
TC5117400BSJ/BST
SYMBOL
PARAMETER
-60 -70 UNIT NOTES
MIN MAX. MIN MAX
tRC
tRMW
tPC
tPRMW
tRAC
tCAC
tAA
tCPA
tCLZ
tOFF
tT
tRP
tRAS
tRASP
tRSH
tRHCP
tCSH
tCAS
tRCD
tRAD
tCRP
tCP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
Random Read or Write Cycle Time
Read-Modify-Write Cycle
Fast Page Mode Cycle Time
Fast Page Mode Read-Modify-Write Cycle Time
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from CAS Precharge
CAS to Output in Low-Z
Output Buffer Turn-off Delay
Transition Time (Rise and Fall)
RAS Precharge Time
RAS Pulse Width
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
RAS Hold Time from CAS
Precharge (Fast Page Mode)
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time
CAS Precharge Time
Row Address Set-Up Time
Row Address Hold Time
Column Address Set-Up Time
Column Address Hold Time
Column Address to RAS Lead Time
Read Command Set-Up Time
Read Command Hold Time
Read Command Hold Time referenced to RAS
110 - 130 -
155 - 180 -
40 - 45 -
85 - 95 -
- 60 - 70
- 15 - 20
- 30 - 35
- 35 - 40
0-0 -
0 15 0 15
3 50 3 50
40 - 50 -
60 10,000 70 10,000
60 200,000 70 200,000
15 - 20 -
35 - 40 -
60 - 70 -
15 10,000 20 10,000
20 45 20 50
15 30 15 35
5-5
10 - 10 -
0-0 -
10 - 10 -
0-0 -
10 - 15 -
30 - 35 -
0-0 -
0-0 -
0-0 -
ns
ns
ns
ns
ns
ns
ns
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9,14,
15
9,14
9,15
9
9
10
8
14
15
11
11
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
5
5 Page 
DR16040794
Write Cycle (OE Controlled Write)
Standard DRAM
TC5117400BSJ/BST-60/70
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet TC5117400BST.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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| TC5117400BSJ-70 | DRAM | Toshiba Semiconductor |
| TC5117400BST | DYNAMIC RAM | Toshiba Semiconductor |
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