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PDF PDU17F Data sheet ( Hoja de datos )
| Número de pieza | PDU17F | |
| Descripción | 7-BIT PROGRAMMABLE DELAY LINE | |
| Fabricantes | Data Delay Devices | |
| Logotipo |  |
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7-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU17F)
PDU17F
data
delay
3
®
devices, inc.
FEATURES
• Digitally programmable in 128 delay steps
• Monotonic delay-versus-address variation
• Two separate outputs: inverting & non-inverting
• Precise and stable delays
• Input & outputs fully TTL interfaced & buffered
• 10 T2L fan-out capability
• Fits standard 40-pin DIP socket
• Auto-insertable
N/C
OUT/
OUT
EN/
GND
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
GND
N/C
EN/
N/C
IN
N/C
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PACKAGES
40 VCC
39 N/C
38 A0
37 A1
36 A2
35 VCC
34 N/C
33 A3
32 A4
31 A5
30 VCC
29 N/C
28 N/C
27 N/C
26 N/C
25 VCC
24 N/C
23 A6
22 N/C
21 N/C
PDU17F-xx
DIP
PDU17F-xxC5
Gull-Wing
PDU17F-xxM
Military DIP
PDU17F-xxMC5
Military Gull-Wing
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU17F-series device is a 7-bit digitally programmable delay line.
IN Delay Line Input
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A6-A0) according to the following formula:
OUT Non-inverted Output
OUT/ Inverted Output
A0-A6 Address Bits
TDA = TD0 + TINC * A
EN/ Output Enable
VCC +5 Volts
where A is the address code, TINC is the incremental delay of the device,
GND Ground
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
• Programmed delay tolerance: 5% or 2ns,
whichever is greater
• Inherent delay (TD0): 13ns typical (OUT)
12ns typical (OUT/)
• Setup time and propagation delay:
Address to input setup (TAIS): 10ns
Disable to output delay (TDISO): 6ns typ. (OUT)
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VCC: 5VDC ± 5%
• Supply current: ICCH = 68ma
ICCL = 86ma
• Minimum pulse width: 8% of total delay
Part
Number
PDU17F-.5
PDU17F-1
PDU17F-2
PDU17F-3
PDU17F-4
PDU17F-5
PDU17F-6
PDU17F-8
PDU17F-10
Incremental Delay
Per Step (ns)
.5 ± .3
1 ± .5
2 ± .5
3 ± 1.0
4 ± 1.0
5 ± 1.5
6 ± 1.5
8 ± 2.0
10 ± 2.0
Total Delay
Change (ns)
63.5 ± 3.2
127 ± 6.4
254 ± 12.7
381 ± 19.1
508 ± 25.4
635 ± 31.8
762 ± 38.1
1,016 ± 50.8
1,270 ± 63.5
NOTE: Any dash number between .5 and 10 not
shown is also available.
©1997 Data Delay Devices
Doc #97005
1/14/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 page  
DELAY LINE AUTOMATED TESTING
PDU17F
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 4.5 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
1 FAST-TTL Gate
5pf ± 10%
1.5V (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
PULSE
GENERATOR
OUT
TRIG
IN DEVICE UNDER OUT
TEST (DUT)
REF
IN
TRIG
TIME INTERVAL
COUNTER
Test Setup
INPUT
SIGNAL
OUTPUT
SIGNAL
TRISE
PWIN
PERIN
TFALL
2.4V VIH 2.4V
1.5V
1.5V
0.6V
0.6V
VIL
TDAR
TDAF
1.5V
VOH
1.5V
Timing Diagram For Testing
VOL
Doc #97005
1/14/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PDU17F.PDF ] | |
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