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PDF PDU1064H Data sheet ( Hoja de datos )
| Número de pieza | PDU1064H | |
| Descripción | ECL-INTERFACED PROGRAMMABLE DELAY LIN | |
| Fabricantes | Data Delay Devices | |
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6-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU1064H)
PDU1064H
data
delay
3
®
devices, inc.
FEATURES
• Digitally programmable in 64 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully 10KH-ECL interfaced & buffered
• Fits 48-pin DIP socket
PIN DESCRIPTIONS
IN Signal Input
OUT Signal Output
A0-A5 Address Bits
ENB Output Enable
VEE -5 Volts
GND Ground
PACKAGES
GND 1 48 GND
ENB 2 47 OUT
A0 7 42 A1
VEE 8 41 A2
GND 9 40 GND
A3
VEE
15 34 A4
16 33 A5
N/C
N/C
OUT
GND
ENB
N/C
N/C
N/C
GND
ENB
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
ENB
IN
1 40
2 39
3 38
4 37
5 36
6 35
7 34
8 33
9 32
10 31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
N/C
N/C
A2
A1
VEE
A0
N/C
A5
A4
VEE
A3
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VEE
N/C
GND 17 32 GND
IN 19
PDU1064H-xxC5 SMD
PDU1064H-xxMC5 Mil SMD
VEE 24
PDU1064H-xx DIP
PDU1064H-xxM Mil DIP
FUNCTIONAL DESCRIPTION
The PDU1064H-series device is a 6-bit digitally programmable delay line. The delay, TDA, from the input
pin (IN) to the output pin (OUT) depends on the address code (A5-A0) according to the following formula:
TDA = TD0 + TINC * A
where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of
the device. The incremental delay is specified by the dash number of the device and can range from
0.5ns through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this
signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain
asserted during normal operation.
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
• Total programmed delay tolerance: 5% or 2ns,
whichever is greater
Inherent delay (TD0): 12ns typical
• Setup time and propagation delay:
Address to input setup (TAIS): 3.6ns
Disable to output delay (TDISO): 1.7ns typical
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VEE: -5VDC ± 5%
• Power Dissipation: 925mw typical (no load)
• Minimum pulse width: 20% of total delay
©1997 Data Delay Devices
Part
Number
PDU1064H-.5
PDU1064H-1
PDU1064H-2
PDU1064H-3
PDU1064H-4
PDU1064H-5
PDU1064H-6
PDU1064H-8
PDU1064H-10
Incremental Delay
Per Step (ns)
0.5 ± 0.3
1.0 ± 0.5
2.0 ± 0.5
3.0 ± 1.0
4.0 ± 1.0
5.0 ± 1.0
6.0 ± 1.0
8.0 ± 1.0
10.0 ± 1.5
Total
Delay (ns)
31.5 ± 2.0
63 ± 3.1
126 ± 6.3
189 ± 9.4
252 ± 12.6
315 ± 15.7
378 ± 18.9
504 ± 25.2
630 ± 31.5
NOTE: Any dash number between .5 and 10
not shown is also available.
Doc #97046
12/17/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 page  
DELAY LINE AUTOMATED TESTING
PDU1064H
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): -5.0V ± 0.1V
Input Pulse:
Standard 10KH ECL
levels
Source Impedance: 50Ω Max.
Rise/Fall Time:
2.0 ns Max. (measured
between 20% and 80%)
Pulse Width:
Period:
PWIN = 1.5 x Total Delay
PERIN = 10 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
50Ω to -2V
5pf ± 10%
(VOH + VOL) / 2
(Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PULSE
GENERATOR
OUT
TRIG
IN DEVICE UNDER OUT
TEST (DUT)
REF
IN
TRIG
OSCILLOSCOPE
ADDRESS SELECT
Test Setup
INPUT
SIGNAL
OUTPUT
SIGNAL
TRISE
PWIN
PERIN
TFALL
80% VIH 80%
50%
50%
20% 20%
VIL
TRISE
TFALL
50%
VOH
50%
Timing Diagram For Testing
VOL
Doc #97046
12/17/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PDU1064H.PDF ] | |
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