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Número de pieza | PDU1032H | |
Descripción | ECL-INTERFACED PROGRAMMABLE DELAY LINE | |
Fabricantes | Data Delay Devices | |
Logotipo | ||
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5-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU1032H)
PDU1032H
FEATURES
• Digitally programmable in 32 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully 10KH-ECL interfaced &
buffered
• Fits 32-pin DIP socket
PACKAGES
GND
ENB
1 32 GND
2 31 OUT
A0
VEE
GND
7 26 A1
8 25 A2
9 24 GND
IN 11
A3
VEE
15
16 17
A4
PDU1032H-xx DIP
PDU1032H-xxM Mil DIP
NC 1
40 NC
NC 2
39 NC
OUT 3
38 A2
GND 4
37 A1
ENB 5
36 VEE
NC 6
35 A0
NC 7
34 NC
NC 8
33 NC
GND 9
32 A4
ENB 10 31 VEE
NC 11 30 A3
NC 12 29 NC
NC 13 28 NC
NC 14 27 NC
NC 15 26 NC
NC 16 25 NC
NC 17 24 NC
GND 18 23 NC
ENB 19 22 VEE
IN 20 21 NC
PDU1032H-xxC5 SMD
PDU1032H-xxMC5 Mil SMD
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU1032H-series device is a 5-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends
on the address code (A4-A0) according to the following formula:
IN Signal Input
OUT Signal Output
A0-A4 Address Bits
TDA = TD0 + TINC * A
ENB Output Enable
VEE -5 Volts
where A is the address code, TINC is the incremental delay of the device,
GND Ground
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 20ns, inclusively. The
enable pin (ENB) is held LOW during normal operation. When this signal is brought HIGH, OUT is forced
into a LOW state. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 2ns,
whichever is greater
• Inherent delay (TD0): 5.5ns typical for dash numbers
up to 5, greater for larger #’s
• Setup time and propagation delay:
Address to input setup (TAIS): 3.6ns
Disable to output delay (TDISO): 1.7ns typical
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VEE: -5VDC ± 5%
• Power Dissipation: 615mw typical (no load)
• Minimum pulse width: 20% of total delay
2003 Data Delay Devices
DASH NUMBER SPECIFICATIONS
Part
Number
PDU1032H-.5
PDU1032H-1
PDU1032H-2
PDU1032H-3
PDU1032H-4
PDU1032H-5
PDU1032H-6
PDU1032H-8
PDU1032H-10
PDU1032H-12
PDU1032H-15
PDU1032H-20
Incremental Delay
Per Step (ns)
0.5 ± 0.3
1.0 ± 0.5
2.0 ± 0.5
3.0 ± 1.0
4.0 ± 1.0
5.0 ± 1.0
6.0 ± 1.0
8.0 ± 1.0
10.0 ± 1.5
12.0 ± 1.5
15.0 ± 1.5
20.0 ± 2.0
Total
Delay (ns)
15.5 ± 2.0
31 ± 2.0
62 ± 3.1
93 ± 4.6
124 ± 6.2
155 ± 7.8
186 ± 9.3
248 ± 12.4
310 ± 15.5
372 ± 18.6
465 ± 23.2
620 ± 31.0
NOTE: Any dash number between .5 and 20
not shown is also available.
Doc #97045
2/25/03
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 page DELAY LINE AUTOMATED TESTING
PDU1032H
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): -5.0V ± 0.1V
Input Pulse:
Standard 10KH ECL
levels
Source Impedance: 50Ω Max.
Rise/Fall Time:
2.0 ns Max. (measured
between 20% and 80%)
Pulse Width:
Period:
PWIN = 1.5 x Total Delay
PERIN = 10 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
50Ω to -2V
5pf ± 10%
(VOH + VOL) / 2
(Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PULSE
GENERATOR
OUT
TRIG
IN DEVICE UNDER OUT
TEST (DUT)
REF
IN
TRIG
OSCILLOSCOPE
ADDRESS SELECT
Test Setup
INPUT
SIGNAL
OUTPUT
SIGNAL
TRISE
PWIN
PERIN
TFALL
80% VIH 80%
50% 50%
20%
20%
VIL
DRISE
50%
VOH
DFALL
50%
Timing Diagram For Testing
VOL
Doc #97045
2/25/03
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
5 Page |
Páginas | Total 5 Páginas | |
PDF Descargar | [ Datasheet PDU1032H.PDF ] |
Número de pieza | Descripción | Fabricantes |
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