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PDF PCF5271 Data sheet ( Hoja de datos )
| Número de pieza | PCF5271 | |
| Descripción | 32-bit Embedded Controller Division | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Hardware Specification
MCF5271EC
Rev. 1.2, 12/2004
MCF5271 Integrated
Microprocessor
Hardware Specification
32-bit Embedded Controller Division
The MCF5271 family is a highly integrated
implementation of the ColdFire® family of reduced
instruction set computing (RISC) microprocessors. This
document describes pertinent features and functions of
the MCF5271 family. The MCF5271 family includes the
MCF5271 and MCF5270 microprocessors. The
differences between these parts are summarized below in
Table 1. This document is written from the perspective of
the MCF5271 and unless otherwise noted, the
information applies also to the MCF5270.
The MCF5271 family combines low cost with high
integration on the popular version 2 ColdFire core with
over 96 (Dhrystone 2.1) MIPS at 100MHz. Positioned
for applications requiring a cost-sensitive 32-bit
solution, the MCF5271 family features a 10/100 Ethernet
MAC and optional hardware encryption to ensure the
application can be connected and protected. In addition,
the MCF5271 family features an enhanced Multiply
Accumulate Unit (eMAC), large on-chip memory (64
Kbytes SRAM, 8 Kbytes configurable cache), and a
32-bit SDR SDRAM memory controller.
Table of Contents
1 MCF5271 Family Configurations ..................... 2
2 Block Diagram ................................................. 2
3 Features .......................................................... 4
4 Signal Descriptions........................................ 12
5 Modes of Operation....................................... 16
6 Design Recommendations ............................ 19
7 Mechanicals/Pinouts and Part Numbers ....... 27
8 Preliminary Electrical Characteristics............ 32
9 Documentation .............................................. 55
Technical Data
© Freescale Semiconductor, Inc., 2004. All rights reserved.
1 page  
Features
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (URTS) and clear-to-send (UCTS) lines for two
UARTs
— Transmit and receive FIFO buffers
• I2C Module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master or slave modes support multiple masters
— Automatic interrupt generation with programmable level
• Queued Serial Peripheral Interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable master bit rates
— Up to 16 pre-programmed transfers
• Four 32-bit DMA Timers
— 20-ns resolution at 50 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input-capture capability with programmable trigger edge on input pin
— Output-compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or reference-compare
— DMA trigger capability on input capture or reference-compare
• Four Periodic Interrupt Timers (PITs)
— 16-bit counter
— Selectable as free running or count down
• Software Watchdog Timer
— 16-bit counter
— Low power mode support
• Frequency Modulated Phase Locked Loop (PLL)
— Crystal or external oscillator reference
— 8 to 25 MHz reference frequency for normal PLL mode
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
Freescale Semiconductor
5
5 Page 
Features
and UARTs. The DMA controller supports single or dual address to off-chip devices or dual address to
on-chip devices.
3.17 External Interface Module (EIM)
The external bus interface handles the transfer of information between the core and memory, peripherals,
or other processing elements in the external address space. Features have been added to support external
Flash modules, for secondary wait states on reads and writes, and a signal to support Active-Low Address
Valid (a signal on most Flash memories).
Programmable chip-select outputs provide signals to enable external memory and peripheral circuits,
providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting
address must be on a boundary that is a multiple of the block size. Each chip select can be configured to
provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data
bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available
for protection from user mode access or read-only access.
3.18 SDRAM Controller
The SDRAM controller provides all required signals for glueless interfacing to a variety of
JEDEC-compliant SDRAM devices. SD_SRAS/SD_SCAS address multiplexing is software configurable
for different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the
address and data buses, SD_RAS, SD_SCAS, SD_WE, SD_CS[1:0] and SD_CKE are dedicated SDRAM
signals.
3.19 Reset
The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the
system, and keep track of what caused the last reset. The power management registers for the internal
low-voltage detect (LVD) circuit are implemented in the reset module. There are six sources of reset:
• External
• Power-on reset (POR)
• Watchdog timer
• Phase locked-loop (PLL) loss of lock
• PLL loss of clock
• Software
External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are also
software-readable status flags indicating the cause of the last reset.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
Freescale Semiconductor
11
11 Page | ||
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| PDF Descargar | [ Datasheet PCF5271.PDF ] | |
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