PDF AD7762 Data sheet ( Hoja de datos )

Número de pieza	AD7762
Descripción	With On-Chip Buffer 625 KSPS
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com 625 kSPS, 24-Bit, 109 dB Σ−Δ ADC With On-Chip Buffer AD7762 FEATURES 120 dB dynamic range at 78 kHz output data rate 109 dB dynamic range at 625 kHz output data rate 112 dB SNR at 78 kHz output data rate 106 dB SNR at 625 kHz output data rate 625 kHz maximum fully filtered output word rate Programmable over-sampling rate (32× to 256×) Fully differential modulator input On-chip differential amplifier for signal buffering Low-pass finite impulse response (FIR) filter with default or user-programmable coefficients Overrange alert bit Digital offset and gain correction registers Filter bypass modes Low power and power-down modes Synchronization of multiple devices via SYNC pin APPLICATIONS Data acquisition systems Vibration analysis Instrumentation GENERAL DESCRIPTION The AD7762 is a high performance, 24-bit Σ-Δ analog-to- digital converter (ADC). It combines wide input bandwidth and high speed with the benefits of Σ-Δ conversion with a performance of 106 dB SNR at 625 kSPS, making it ideal for high speed data acquisition. Wide dynamic range combined with significantly reduced antialiasing requirements simplify the design process. An integrated buffer to drive the reference, a differential amplifier for signal buffering and level shifting, an overrange flag, internal gain and offset registers, and a low-pass digital FIR filter make the AD7762 a compact, highly integrated data acquisition device requiring minimal peripheral com- ponent selection. In addition, the device offers programmable decimation rates, and the digital FIR filter can be adjusted if the default characteristics are not appropriate to the application. The AD7762 is ideal for applications demanding high SNR without a complex front end signal processing design. The differential input is sampled at up to 40 MSPS by an analog modulator. The modulator output is processed by a series of low- pass filters, the final filter having default or user-programmable FUNCTIONAL BLOCK DIAGRAM VIN– VIN+ VREF+ BUF DIFF MCLK SYNC RESET AD7762 CONTROL LOGIC I/O OFFSET AND GAIN REGISTERS MULTIBIT Σ-Δ MODULATOR RECONSTRUCTION PROGRAMMABLE DECIMATION FIR FILTER ENGINE AVDD1 AVDD2 AVDD3 AVDD4 DECAPA/B RBIAS AGND VDRIVE DVDD DGND CS RD/WR DRDY DB0 TO DB15 Figure 1. coefficients. The sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7762. The reference voltage supplied to the AD7762 determines the analog input range. With a 4 V reference, the analog input range is ±3.2 V differential biased around a common mode of 2 V. This common-mode biasing can be achieved using the on-chip differential amplifier, further reducing the external signal conditioning requirements. The AD7762 is available in an exposed paddle, 64-lead TQFP and is specified over the industrial temperature range from −40°C to +85°C. Table 1. Related Devices Part No. Description AD7760 24-bit, 2.5 MSPS, 100 dB Σ-Δ, parallel interface AD7763 24-bit, 625 kSPS, 109 dB Σ-Δ, serial interface Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. 1 page TIMING SPECIFICATIONS AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted. Table 3. Parameter fMCLK fICLK t11, 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Limit at TMIN, TMAX 1 40 500 20 0.5 × tICLK 10 3 (0.5 × tICLK) + 16 ns tICLK tICLK 3 11 4 × tICLK 4 × tICLK 5 0 Unit MHz min MHz max kHz min MHz max typ ns min ns min max min min ns min ns max min min ns min ns min Description Applied master clock frequency Internal modulator clock derived from MCLK DRDY pulse width DRDY falling edge to CS falling edge RD/WR setup time to CS falling edge Data access time CS low read pulse width CS high pulse width between reads RD/WR hold time to CS rising edge Bus relinquish time CS low write pulse width CS high period between address and data Data setup time Data hold time 1 tICLK = 1/fICLK. 2 When ICLK = MCLK, DRDY pulse width depends on the mark/space ratio of applied MCLK. TIMING DIAGRAMS DRDY CS RD/WR D[0:15] t1 t2 t5 t3 t4 DATA MSW t6 t7 LSW + STATUS t8 Figure 2. Parallel Interface Timing Diagram CS RD/WR D[0:15] t11 t9 t10 REGISTER ADDRESS t12 Figure 3. AD7762 Register Write REGISTER DATA Rev. 0 \| Page 5 of 28 AD7762 5 Page 0 –25 –50 –75 –100 –125 –150 –175 –200 0 60000 120000 180000 FREQUENCY (Hz) 240000 300000 Figure 11. Normal Mode FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation 0 –25 –50 –75 –100 –125 –150 –175 –200 0 60000 120000 180000 FREQUENCY (Hz) 240000 300000 Figure 12. Normal Mode FFT, 100 kHz, −6 dB Input Tone, 32× Decimation 120 118 –60dB 116 114 –6dB 112 –0.5dB 110 108 106 0 64 128 192 DECIMATION RATE (x) 256 Figure 13. Normal Mode SNR vs. Decimation Rate, 1 kHz Input Tone AD7762 0 –25 –50 –75 –100 –125 –150 –175 –200 0 60000 120000 180000 FREQUENCY (Hz) 240000 300000 Figure 14. Low Power FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation 0 –25 –50 –75 –100 –125 –150 –175 –200 0 60000 120000 180000 FREQUENCY (Hz) 240000 300000 Figure 15. Low Power FFT, 100 kHz, −6 dB Input Tone, 32× Decimation 116 –60dB 112 –6dB –0.5dB 108 104 0 64 128 192 DECIMATION RATE (x) 256 Figure 16. Low Power SNR vs. Decimation Rate, 1 kHz Input Tone Rev. 0 \| Page 11 of 28 11 Page

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