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PDF AD7356 Data sheet ( Hoja de datos )
| Número de pieza | AD7356 | |
| Descripción | SAR ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
FEATURES
Dual 12-bit SAR ADC
Simultaneous Sampling
Throughput rate: 5 MSPS Per Channel
Specified for VDD of 2.5 V
No latency to 12 bits
Power dissipation:
35 mW at 5 MSPS
On-chip reference:
2.048 V ± 0.5% max @ 25°C, 10ppm/°C
Dual conversion with read
High speed serial interface:
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
−40°C to +125°C operation
Shutdown mode: 10 µA max
16-lead TSSOP package
GENERAL DESCRIPTION
The AD73561 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.5 V power supply
and features throughput rates up to 5 MSPS. The part contains two
ADCs, each preceded by a low noise, wide bandwidth track-and-
hold circuit that can handle input frequencies in excess of
200 MHz.
The conversion process and data acquisition use standard control
inputs allowing for easy interfacing to microprocessors or DSPs.
The input signal is sampled on the falling edge of CS; conversion is
also initiated at this point. The conversion time is determined by
the SCLK frequency.
The AD7356 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 2.5 V supply and
a 5 MSPS throughput rate, the part consumes 14 mA typically. The
part also offers flexible power/throughput rate management when
operating in normal mode as the quiescent current consumption is
so low.
The analog input range for the parts is the differential common
mode +/- Vref/2. The AD7356 has an on-chip 2.048 V reference
that can be overdriven when an external reference is preferred.
The AD7356 is available in a 16-lead thin shrink small outline
package (TSSOP).
Differential Input, Dual,
5 MSPS, 12-Bit, SAR ADC
AD7356
FUNCTIONAL BLOCK DIAGRAM
Vdd Vdrive
AD7356
VINA+
VINA-
12-BIT
T/H SUCCESSIVE
APPROXIMATION
ADC
SDATAA
REF
BUF
BUF
CONTROL
LOGIC
SCLK
CS
VINB+
VINB-
12-BIT
SUCCESSIVE
T/H APPROXIMATION
ADC
SDATAB
AGND AGND REFGND DGND
Figure 1.
PRODUCT HIGHLIGHTS
1. Two Complete ADC Functions Allow Simultaneous Sampling
and Conversion of Two Channels.
The conversion result of both channels is simultaneously
available on separate data lines or in succession on one data
line if only one serial port is available.
2. High Throughput with Low Power Consumption.
The AD7356 offers a 5 MSPS throughput rate with 35 mW
power consumption.
3. The parts feature two standard successive approximation
ADCs with accurate control of the sampling instant via a
CS input and once off conversion control.
1 Protected by U.S. Patent No. 6,681,332
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
AD7356
TIMING SPECIFICATIONS
VDD = 2.5 V, VDRIVE = 2.5 V to 3.3 V, internal reference = 2.048 V, TA = TMAX to TMIN1, unless otherwise noted.
Table 2.
Parameter
fSCLK
tCONVERT
tQUIET
t2
t3
t42
t5
t6
t7
t8
t9
t10
Latency
Limit at TMIN, TMAX
Unit
50 kHz min
80 MHz max
t2 +13 × tSCLK
5
ns max
ns min
5 ns min
TBD ns max
TBD ns max
0.40 tSCLK
0.40 tSCLK
TBD
ns min
ns min
ns min
TBD ns max
TBD ns min
TBD ns min
TBD ns max
No Latency
Description
AD7356, 12 bit resolution, tSCLK = 1/fSCLK
Minimum time between end of serial read and next falling edge of CS
CS to SCLK setup time
Delay from CS until DOUTA and DOUTB are three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
CS rising edge to DOUTA, DOUTB, high impedance
CS rising edge to falling edge pulse width
SCLK falling edge to DOUTA, DOUTB, high impedance
SCLK falling edge to DOUTA, DOUTB, high impedance
1 Temperature ranges are as follows: Y Grade: −40°C to +125°C, B Grade: −40°C to +85°C.
2 The time required for the output to cross 0.4 V or 2.4 V.
Rev. PrC | Page 5 of 18
5 Page 
Preliminary Technical Data
AD7356
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7356 is a fast, dual, 12-bit, single-supply, successive
approximation analog-to-digital converter. The part operates
from a 2.5 V power supply and features throughput rates up to
5MSPS.
The AD7356 contains two on-chip differential track-and-hold
amplifiers, two successive approximation analog-to-digital
converters and a serial interface with two separate data output
pins. They part is housed in a 16-lead TSSOP package, offering
the user considerable space-saving advantages over alternative
solutions.
The serial clock input accesses data from the part, but also
provides the clock source for each successive approximation
ADC. The AD7356 has an on-chip 2.048V reference. If an
external reference is desired the internal reference can be
overdriven with a reference of value ranging from (2.048V +
100mV) to Vdd. If the internal reference is to be used elsewhere
in the system, then the reference output needs to be buffered
first. The differential analog input range for the AD7356 is VCM
± VREF∕2.
The AD7356 features power-down options to allow power
saving between conversions. The power-down feature is
implemented via the standard serial interface, as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7356 has two successive approximation analog-to-
digital converters, each based around two capacitive DACs.
Figure 8 and Figure 9 show simplified schematics of one of
these ADCs in acquisition and conversion phase, respectively.
The ADC is comprised of control logic, a SAR, and two
capacitive DACs. In Figure 8 (the acquisition phase), SW3 is
closed, SW1 and SW2 are in position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays may
acquire the differential signal on the input.
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the VIN+ and VIN- pins must be matched,
otherwise, the two inputs will have different settling times,
resulting in errors.
VIN+
VIN–
B CS
A SW1
A SW2
B
CS
VREF
CAPACITIVE
DAC
COMPARATOR
SW3
CONTROL
LOGIC
CAPACITIVE
DAC
Figure 9. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7356 is straight binary. The
designed code transitions occur at successive LSB values (1 LSB,
2 LSBs and so on). The LSB size is (2 ×VREF)/4096 for the
AD7356. The ideal transfer characteristic of the AD7356 is
shown in Figure 10.
111...111
111...110
111...101
VIN+
VIN–
B CS
A SW1
A SW2
CS
B
VREF
CAPACITIVE
DAC
COMPARATOR
SW3
CONTROL
LOGIC
CAPACITIVE
DAC
Figure 8. ADC Acquisition Phase
When the ADC starts a conversion (Figure 9), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
000...010
000...001
000...000
–VREF+1 LSB
+VREF–1 LSB
–VREF+0.5 LSB
+VREF–1.5 LSB
ANALOG INPUT
Figure 10. AD7356 Ideal Transfer Characteristic
ANALOG INPUT STRUCTURE
Figure 11 shows the equivalent circuit of the analog input
structure of the AD7356. The four diodes provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signals never exceed the supply rails by
more than 300mV. This causes these diodes to become forward-
biased and start conducting into the substrate. These diodes can
Rev. PrC | Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AD7356.PDF ] | |
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