IDT709149S Datasheet PDF - IDT
| Part Number | IDT709149S | |
| Description | HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM | |
| Manufacturers | IDT | |
| Logo |  |
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HIGH-SPEED 36K (4K x 9-BIT)
SYNCHRONOUS PIPELINED
DUAL-PORT SRAM
IDT709149S
Features
x Architecture based on Dual-Port SRAM cells
Allows full simultaneous access from both ports
x High-speed clock-to-data output times
Commercial: 8/10/12ns (max.)
x Low-power operation
IDT709149S
Active: 1500mW (typ.)
Standby: 75mW (typ.)
x 4K X 9 bits
x Synchronous operation
4ns setup to clock, 1ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 8ns clock to data out
x 13ns cycle time, 76MHz operation in pipeline mode
Self-timed write allows for fast cycle times
x TTL-compatible, singles 5V (±10%) power supply
x Clock Enable feature
x Guaranteed data output hold times
x Industrial temperature range (40°C to +85°C) is available
for selected speeds.
Description
The IDT709149 is a high-speed 4K x 9 bit synchronous Dual-Port
SRAM. The memory array is based on Dual-Port memory cells to allow
simultaneous access from both ports. Registers on control, data, and
address inputs provide low set-up and hold times. The timing latitude
provided by this approach will allow systems to be designed with very
Functional Block Diagram
I/O0-8L
OEL
CLKL
CLKENL
R/WL
CEL
REG
WRITE
LOGIC
MMYAAREERRMMRAOOAYRRYY
WRITE
LOGIC
SENSE
SENSE
AMPS DECODER DECODER AMPS
I/O0-8R
FT/PIPEDR
0/1
0
1
REG
en
REG
en
Self-
timed
Write
Logic
A0L-A11L A0R-A11R
Self-
timed
Write
Logic
OER
CLKR
CLKENR
REG
R/WR
CER
3494 drw 01
©1999 Integrated Device Technology, Inc.
1
SEPTEMBER 1999
DSC-3494/4
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IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(4)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
709149S8
Com'l Only
709149S10
Com'l Only
709124S12
Com'l Only
Symbol
tCY C1
tCY C2
tCH1
tCL1
tCH2
tCL2
tCD1
tCD2
Parameter
Clock Cycle Time (Flow-Through)(3)
Clock Cycle Time (Pipelined)(3)
Clock High Time (Flow-Through)(3)
Clock Low Time (Flow-Through)(3)
Clock High Time (Pipelined)(3)
Clock Low Time (Pipelined)(3)
Clock to Data Valid (Flow-Through)(3)
Clock to Data Valid (Pipelined)(3)
Min.
16
13
6
6
6
6
____
____
Max.
____
____
____
____
____
____
12
8
Min.
20
15
7
7
6
6
____
____
Max.
____
____
____
____
____
____
15
10
Min.
20
16
8
8
6
6
____
____
Max.
____
____
____
____
____
____
20
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tS Registered Signal Set-up Time
4 ____ 4 ____ 5 ____ ns
tH Registered Signal Hold Time
1 ____
1 ____
1 ____ ns
tDC
tCKL Z
tCK HZ
Data Output Hold After Clock High
Clock High to Output Low-Z(1,2)
Clock High to Output High-Z(1,2)
1 ____
1 ____
1 ____ ns
2 ____ 2 ____ 2 ____ ns
____ 7 ____ 7 ____ 9 ns
tOE Output Enable to Output Valid
tOLZ Output Enable to Output Low-Z(1,2)
tOHZ Output Disable to Output High-Z(1,2)
____ 8 ____ 8 ____ 10 ns
0 ____ 0 ____ 0 ____ ns
____ 7 ____ 7 ____ 9 ns
tSCK Clock Enable, Disable Set-Up Time
4 ____ 4 ____ 5 ____ ns
tHCK Clock Enable, Disable Hold Time
1 ____
1 ____
1 ____ ns
tCWDD
Write Port Clock High to Read Data Delay
____ 25 ____ 30 ____ 35 ns
NOTES:
3494 tbl 08
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The Pipelined output parameters (tCYC2, tCD2) always apply to the Left Port. The Right Port uses the Pipelined tCYC2 and tCD2 when FT/PIPEDR = VIH and the Flow-
Through parameters (tCYC1, tCD1) when FT/PIPEDR = VIL.
4. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.542
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