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PDF HY29DS322 Data sheet ( Hoja de datos )
| Número de pieza | HY29DS322 | |
| Descripción | (HY29DS322 / HY29DS323) Simultaneous Read/Write Flash Memory | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY29DS322/HY29DS323
32 Megabit (4M x 8/2M x16) Super-Low Voltage,
Dual Bank, Simultaneous Read/Write, Flash Memory
KEY FEATURES
n Single Power Supply Operation
− Read, program, and erase operations
from 1.8 to 2.2 V (2.0V ± 10%)
− Ideal for battery-powered applications
n Simultaneous Read/Write Operations
− Host system can program or erase in one
bank while simultaneously reading from any
sector in the other bank with zero latency
between read and write operations
n High Performance
− 100, 110 and 120 ns access time versions
n Ultra Low Power Consumption (Typical
Values)
− Automatic sleep mode current: 5 µA
− Standby mode current: 5 µA
− Read current: 5 mA (at 5 MHz)
− Program/erase current: 20 mA
n Boot-Block Sector Architecture with 71
Sectors in Two Banks for Fast In-System
Code Changes
n Secured Sector: An Extra 64 Kbyte Sector
that Can Be:
− Factory locked and identifiable: 16 bytes
available for a secure, random factory
Electronic Serial Number
− Customer lockable: Can be read, program-
med, or erased just like other sectors
n Flexible Sector Architecture
− Sector Protection allows locking of a
sector or sectors to prevent program or
erase operations within that sector
− Temporary Sector Unprotect allows
changes in locked sectors (requires high
voltage on RESET# pin)
n Automatic Erase Algorithm Erases Any
Combination of Sectors or the Entire Chip
n Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
n Compliant with Common Flash Memory
Interface (CFI) Specification
n Minimum 100,000 Write Cycles per Byte/
Word
n Compatible with JEDEC Standards
− Pinout and software compatible with
single-power supply Flash devices
− Superior inadvertent write protection
n Data# Polling and Toggle Bits
− Provide software confirmation of completion
of program or erase operations
n Ready/Busy# Pin
− Provides hardware confirmation of
completion of program or erase operations
n Erase Suspend
− Suspends an erase operation to allow
programming data to or reading data from
a sector in the same bank
− Erase Resume can then be invoked to
complete the suspended erasure
n Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
n WP#/ACC Input Pin
− Write protect (WP#) function allows
hardware protection of two outermost boot
sectors, regardless of sector protect status
− Acceleration (ACC) function provides
accelerated program times
n Fast Program and Erase Times
− Sector erase time: 2 sec typical
− Byte/Word program time utilizing
Acceleration function: 10 µs typical
n Space Efficient Packaging
− 48-pin TSOP and 48-ball FBGA
packages
LOGIC DIAGRAM
21
A[20:0]
CE#
OE#
WE#
DQ[14:0]
DQ[15]/A[-1]
WP#/ACC
RY/BY#
RESET#
BYTE#
15
Product Brief May 2001
1 page  
PIN CONFIGURATIONS
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
A[8]
A[19]
A[20]
WE#
RESET#
NC
WP#/ACC
RY/BY#
A[18]
A[17]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TSOP48
HY29DS322/HY29DS323
48 A[16]
47 BYTE#
46 VSS
45 DQ[15]/A[-1]
44 DQ[7]
43 DQ[14]
42 DQ[6]
41 DQ[13]
40 DQ[5]
39 DQ[12]
38 DQ[4]
37 VCC
36 DQ[11]
35 DQ[3]
34 DQ[10]
33 DQ[2]
32 DQ[9]
31 DQ[1]
30 DQ[8]
29 DQ[0]
28 OE#
27 VSS
26 CE#
25 A[0]
PB May 01
48-Ball FBGA - Top View, Balls Facing Down
C7
A[13]
D7
A[12]
E7
A[14]
C6 D6 E6
A[9] A[8] A[10]
C5 D5 E5
WE# RESET# NC
C4 D4 E4
RY/BY# WP#/ACC A[18]
C3 D3 E3
A[7] A[17] A[6]
C2 D2 E2
A[3] A[4] A[2]
F7
A[15]
F6
A[11]
F5
A[19]
F4
A[20]
F3
A[5]
F2
A[1]
G7 H7 J7 K7
A[16]
VIH DQ[15] VSS
G6 H6 J6 K6
DQ[7] DQ[14] DQ[13] DQ[6]
G5 H5 J5 K5
DQ[5] DQ[12] VCC DQ[4]
G4 H4 J4 K4
DQ[2] DQ[10] DQ[11] DQ[3]
G3 H3 J3 K3
DQ[0] DQ[8] DQ[9] DQ[1]
G2 H2 J2 K2
A[0] CE# OE# VSS
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet HY29DS322.PDF ] | |
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