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Hynix Semiconductor - (HY29DL162 / HY29DL163) Simultaneous Read/Write Flash Memory

Numéro de référence HY29DL163
Description (HY29DL162 / HY29DL163) Simultaneous Read/Write Flash Memory
Fabricant Hynix Semiconductor 
Logo Hynix Semiconductor 





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HY29DL163 fiche technique
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HY29DL162/HY29DL163
16 Megabit (2M x 8/1M x16) Low Voltage,
Dual Bank, Simultaneous Read/Write Flash Memory
KEY FEATURES
n Single Power Supply Operation
Read, program, and erase operations
from 2.7 to 3.6 V
Ideal for battery-powered applications
n Simultaneous Read/Write Operations
Host system can program or erase in one
bank while simultaneously reading from any
sector in the other bank with zero latency
between read and write operations
n High Performance
70 and 80 ns access time versions with
30pF load
90 and 120 ns access time versions with
100pF load
n Ultra Low Power Consumption (Typical
Values)
Automatic sleep mode current: 200 nA
Standby mode current: 200 nA
Read current: 10 mA (at 5 MHz)
Program/erase current: 15 mA
n Boot-Block Sector Architecture with 39
Sectors in Two Banks for Fast In-System
Code Changes
n Secured Sector: An Extra 64 Kbyte Sector
that Can Be:
Factory locked and identifiable: 16 bytes
available for a secure, random factory-
programmed Electronic Serial Number
Customer lockable: Can be read, program-
med, or erased just like other sectors
n Flexible Sector Architecture
Sector Protection allows locking of a
sector or sectors to prevent program or
erase operations within that sector
Temporary Sector Unprotect allows
changes in locked sectors (requires high
voltage on RESET# pin)
n Automatic Erase Algorithm Erases Any
Combination of Sectors or the Entire Chip
n Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
n Compliant with Common Flash Memory
Interface (CFI) Specification
n Minimum 100,000 Write Cycles per Sector
(1,000,000 cycles Typical)
n Compatible with JEDEC Standards
Pinout and software compatible with
single-power supply Flash devices
Superior inadvertent write protection
n Data# Polling and Toggle Bits
Provide software confirmation of completion
of program or erase operations
n Ready/Busy# Pin
Provides hardware confirmation of
completion of program or erase operations
n Erase Suspend
Suspends an erase operation to allow
programming data to or reading data from
a sector in the same bank
Erase Resume can then be invoked to
complete the suspended erasure
n Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
n WP#/ACC Input Pin
Write protect (WP#) function allows
hardware protection of two outermost boot
sectors, regardless of sector protect status
Acceleration (ACC) function provides
accelerated program times
n Fast Program and Erase Times
Sector erase time: 0.5 sec typical
Byte/Word program time utilizing
Acceleration function: 10 µs typical
n Space Efficient Packaging
48-pin TSOP and 48-ball FBGA packages
LOGIC DIAGRAM
20
A[19:0]
DQ[7:0]
CE#
OE#
WE#
RESET#
BYTE#
DQ[14:8]
DQ[15]/A[-1]
WP#/ACC
RY/BY#
8
7
Preliminary
Revision 1.3, June 2001

PagesPages 30
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