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PDF IDT70T9169 Data sheet ( Hoja de datos )
| Número de pieza | IDT70T9169 | |
| Descripción | (IDT70T9159L / IDT70T9169) HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
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HIGH-SPEED 2.5V
16/8K X 9 SYNCHRONOUS
PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
IDT70T9169/59L
.eatures
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed clock to data access
– Commercial:7.5/9/12ns (max.)
– Industrial: 9ns (max.)
x Low-power operation
– IDT70T9169/59L
Active: 225mW (typ.)
Standby: 1.5mW (typ.)
x Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
x Counter enable and reset features
x Dual chip enables allow for depth expansion without
additional logic
.unctional Block Diagram
x Full synchronous operation on both ports
– 4.0ns setup to clock and 0.5ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
x LVTTL- compatible, single 2.5V (±100mV) power supply
x Industrial temperature range (–40°C to +85°C) is
available for 66MHz
x Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
A13L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
NOTE:
1. A13 is a NC for IDT70T9159.
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
FT/PIPER
I/O0R - I/O8R
A13R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5654 drw 01
©2002 Integrated Device Technology, Inc.
1
JULY 2002
DSC-5654/1
1 page  
IDT70T9169/59L
High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control(1,2)
External
Address
Previous Internal
Internal Address
Address Used
CLK
ADS CNTEN CNTRST
I/O(3)
MODE
An X An ↑ L(4) X H DI/O (n) External Address Used
X
An An + 1 ↑ H L(5)
H DI/O(n+1) Counter Enabled—Internal Address generation
X An + 1 An + 1 ↑ H H
H DI/O(n+1) External Addre ss Blocked—Counter disab led (An + 1 reused)
X X A0 ↑ X X L(4) DI/O(0) Counter Reset to Address 0
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
5654 tbl 03
Recommended Operating
Temperature and Supply Voltage
Grade
Ambient
Temperature(1)
GND
VDD
Commercial
0OC to +70OC
0V 2.5V + 100mV
Industrial
-40OC to +85OC
0V 2.5V + 100mV
NOTES:
5654 tbl 04
1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating
Conditions
S ym bo l
P ara m e ter
Min. Typ.
M ax.
Unit
V DD Sup p ly Vo ltag e
2.4 2.5 2.6 V
V SS G ro und
00 0 V
V IH Inp ut Hig h Vo ltag e
1.7 ____ V DD+ 0.3V (2) V
V IL Inp ut Lo w Vo ltag e
-0 . 3 (1)
____
0.7
V
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDD +0.3V.
5654 tbl 05
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect to
GND
-0.5 to +3.6
V
TBIAS
Temperature
Under Bias
-55 to +125
oC
TSTG Storage
Temperature
-65 to +150
oC
IOUT DC Output Current
50 mA
NOTES:
5654 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
Capacitance(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions(2)
Max. Unit
CIN Input Capacitance
COUT(3) Output Capacitance
VIN = 3dV
VOUT = 3dV
9 pF
10 pF
NOTES:
5654 tbl 07
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
6.542
5 Page 
IDT70T9169/59L
High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2 tCL2
CLK
CE0
tSC tHC
CE1
R/W tSW tHW
tSW tHW
ADDRESS(4)
DATAIN
DATAOUT
An
tSA tHA
An +1
tCD2
(2)
READ
An + 2
An + 2
tSD tHD
An + 3
Dn + 2
tCKHZ(1)
Qn
NOP(5)
WRITE
An + 4
tCKLZ(1) tCD2
Qn + 3
READ
5654 drw 11
Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2 tCL2
CLK
CE0
CE1
R/W
tSC tHC
tSW tHW
tSW tHW
ADDRESS(4)
DATAIN
DATAOUT
An
tSA tHA
(2)
An +1
An + 2
tSD tHD
Dn + 2
tCD2
Qn
tOHZ(1)
An + 3
Dn + 3
An + 4
An + 5
tCKLZ(1)
tCD2
Qn + 4
OE
READ
WRITE
READ
5654 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.412
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet IDT70T9169.PDF ] | |
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