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PDF EN27C010 Data sheet ( Hoja de datos )
| Número de pieza | EN27C010 | |
| Descripción | 1Megabit EPROM | |
| Fabricantes | EON | |
| Logotipo |  |
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EN27C010 1Megabit EPROM (128K x 8)
EN27C010
FEATURES
• Fast Read Access Time:
-45, -55, -70, and -90ns
• Single 5V Power Supply
• Programming Voltage +12.75V
• QuikRiteTM Programming Algorithm
• Typical programming time 20µs
• Low Power CMOS Operation
• 1µA Standby (Typical)
• 30mA Operation (Max.)
• CMOS- and TTL-Compatible I/O
• High-Reliability CMOS Technology
• Latch-Up Immunity to 100mA
from -1V to VCC + 1V
• Two-Line Control ( OE & CE )
• Standard Product Identification Code
• JEDEC Standard Pinout
• 32-pin PDIP
• 32-pin PLCC
• 32-pin TSOP (Type 1)
• Commercial and Industrial Temperature
Ranges
GENERAL DESCRIPTION
The EN27C010 is a low-power 1-Megabit, 5V-only one-time-programmable (OTP) read-only
memory (EPROM). Organized into 128K words with 8 bits per word, it features QuikRiteTM single-
address location programming, typically at 20µs per byte. Any byte can be accessed in less than
45ns, eliminating the need for WAIT states in high-performance microprocessor systems. The
EN27C010 has separate Output Enable ( OE ) and Chip Enable ( CE ) controls which eliminate
bus contention issues.
FIGURE 1. PDIP
PDIP Top View
Pin Name
A0-A16
DQ0-DQ7
CE
OE
PGM
NC
Function
Addresses
Outputs
Chip Enable
Output Enable
Program Strobe
No Connect
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 PGM
30 NC
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
1
Tel: 408-235-8680
Fax: 408-235-8685
1 page  
EN27C010
READ MODE
The EN27C010 has two control functions, both of which must be logically satisfied in order to
obtain data at the outputs. Chip Enable ( CE ) is the power control and should be used for
device selection. Output Enable ( OE ) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that addresses are stable,
address access time (tACC) is equal to the delay from CE to output (tCE) . Data is available at
the outputs (tOE) after the falling edge of OE , assuming the CE has been LOW and
addresses have been stable for at least tACC - tOE.
STANDBY MODE
The EN27C010 has CMOS standby mode which reduces the maximum VCC current to 20µA.
It is placed in CMOS standby when CE is at VCC ± 0.3 V. The EN27C010 also has a TTL-
standby mode which reduces the maximum VCC current to 1.0 mA. It is placed in TTL-
standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance
state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-line control function is provided to allow
for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that CE be decoded and used as the primary device-selection function,
while OE be made a common connection to all devices in the array and connected to the READ
line from the system control bus. This assures that all deselected memory devices are in their
low-power standby mode and that the output pins are only active when data is desired from a
particular memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced
on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks
is dependent on the output capacitance loading of the device. At a minimum, a 0.1µF ceramic
capacitor (high frequency, low inherent inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused
by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7µF bulk
electrolytic capacitor should be used between VCC and VSS for each eight devices. The
location of the capacitor should be close to where the power supply is connected to the array.
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
5
Tel: 408-235-8680
Fax: 408-235-8685
5 Page 
EN27C010
FIGURE 8. PROGRAMMING WAVEFORMS
ADDRESS
DATA
VCC
VPP
CE
PGM
OE
VIH
VIL
VIH
VIL
6.5V
5.0V
PROGRAM
ADDRESS STABLE
tAS tOE
DATA IN
tDS
tDH
tVCS
13.0V
5.0V
tPRT
VIH
VIL
tVPS
tCES
VIH
VIL
tPW
VIH
VIL
tOES
READ
(VERIFY)
DATA OUT
VALID
tAH
tDFP
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
11
Tel: 408-235-8680
Fax: 408-235-8685
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet EN27C010.PDF ] | |
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