PDF HY5DU56822BT-D4 Data sheet ( Hoja de datos )

Número de pieza	HY5DU56822BT-D4
Descripción	(HY5DU56x22BT-D4x) 256M-P DDR SDRAM
Fabricantes	Hynix Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de HY5DU56822BT-D4 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! www.DataSheet4U.com HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 256M-P DDR SDRAM HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Aug. 2003 1 page PIN DESCRIPTION PIN CK, /CK TYPE Input CKE Input /CS BA0, BA1 Input Input A0 ~ A12 Input /RAS, /CAS, /WE Input DM Input DQS DQ VDD/VSS VDDQ/VSSQ VREF NC I/O I/O Supply Supply Supply NC HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 DESCRIPTION Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied. Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com- mands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE- CHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. Data input / output pin : Data bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. Rev. 0.4 / Aug. 2003 5 5 Page OPERATION COMMAND TRUTH TABLE-II HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Current State WRITE READ WITH AUTOPRE- CHARGE WRITE AUTOPRE- CHARGE PRE- CHARGE /CS /RAS /CAS /WE L L HH L LHL L L LH LLLL HXXX L HHH L HHL LHLH LHLL L L HH L LHL L L LH LLLL HXXX L HHH L HHL LHLH LHLL L L HH L LHL L L LH LLLL HXXX L HHH L HHL LHLH LHLL L L HH L LHL L L LH LLLL Address BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP-Enter IDLE after tRP NOP-Enter IDLE after tRP ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,10 NOP-Enter IDLE after tRP ILLEGAL11 ILLEGAL11 Rev. 0.4 / Aug. 2003 11 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet HY5DU56822BT-D4.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
HY5DU56822BT-D4	(HY5DU56x22BT-D4x) 256M-P DDR SDRAM	Hynix Semiconductor
HY5DU56822BT-D43	(HY5DU56x22BT-D4x) 256M-P DDR SDRAM	Hynix Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar