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PDF DS26528 Data sheet ( Hoja de datos )
| Número de pieza | DS26528 | |
| Descripción | Octal T1/E1/J1 Transceiver | |
| Fabricantes | Maxim Integrated Products | |
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GENERAL DESCRIPTION
The DS26528 is a single-chip 8-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each port is independently configurable,
supporting both long-haul and short-haul lines.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
T1/E1/J1
NETWORK
DS26528
T1/J1/E1
Transceiver
x8
BACKPLANE
TDM
DS26528
Octal T1/E1/J1 Transceiver
FEATURES
§ Eight Complete T1, E1, or J1 Long-Haul/Short-
Haul Transceivers (LIU plus Framer)
§ Independent T1, E1, or J1 Selections for Each
Transceiver
§ Internal Software-Selectable Transmit- and
Receive-Side Termination for 100W T1 Twisted
Pair, 110W J1 Twisted Pair, 120W E1 Twisted
Pair, and 75W E1 Coaxial Applications
§ Crystal-Less Jitter Attenuators can be Selected
for Transmit or Receive Path. The Jitter
Attenuator meets ETSI CTR 12/13, ITU G.736,
G.742, G.823, and AT&T PUB 62411.
§ External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
operation. This Clock is Internally Adapted for T1
or E1 Usage in the Host Mode.
§ Receive Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
§ Transmit Open and Short Circuit Detection
§ LIU LOS in Accordance with G.775, ETSI
300233, and T1.231
§ Transmit Synchronizer
§ Flexible Signaling Extraction and Insertion Using
Either the System Interface or Microprocessor
Port
§ Alarm Detection and Insertion
§ T1 Framing Formats of D4, SLC-96, and ESF
§ J1 Support
§ E1 G.704 and CRC-4 Multiframe
§ T1 to E1 Conversion
Features continued in Section 2.
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS26528
-40°C to +85°C 256 TE-CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 012405
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DS26528 Octal T1/E1/J1 Transceiver
Figure 13-5. Receive Framer Timing—Backplane (T1 Mode) .............................................................. 252
Figure 13-6. Receive Side Timing, Elastic Store Enabled (T1 Mode)................................................... 253
Figure 13-7. Receive Framer Timing—Line Side ................................................................................. 253
Figure 13-8. Transmit Formatter Timing—Backplane .......................................................................... 255
Figure 13-9. Transmit Formatter Timing, Elastic Store Enabled........................................................... 256
Figure 13-10. Transmit Formatter Timing—Line Side .......................................................................... 256
Figure 13-11. JTAG Interface Timing Diagram .................................................................................... 257
Figure 14-1. JTAG Functional Block Diagram...................................................................................... 259
Figure 14-2. Tap Controller State Diagram .......................................................................................... 262
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5 Page 
DS26528 Octal T1/E1/J1 Transceiver
2.8 Test and Diagnostics
§ IEEE 1149.1 Support
§ Per-channel programmable on-chip bit error-rate testing (BERT)
§ Pseudorandom patterns including QRSS
§ User-defined repetitive patterns
§ Daly pattern
§ Error insertion single and continuous
§ Total-bit and errored-bit counts
§ Payload error insertion
§ Error insertion in the payload portion of the T1 frame in the transmit path
§ Errors can be inserted over the entire frame or selected channels
§ Insertion options include continuous and absolute number with selectable insertion rates
§ F-bit corruption for line testing
§ Loopbacks (remote, local, analog, and per-channel loopback)
2.9 Control Port
§ 8-bit parallel control port
§ Intel or Motorola nonmultiplexed support
§ Flexible status registers support polled, interrupt, or hybrid program environments
§ Software reset supported
§ Hardware reset pin
§ Software access to device ID and silicon revision
3. APPLICATIONS
The DS26528 is useful in applications such as:
§ Routers
§ Channel Service Units (CSUs)
§ Data Service Units (DSUs)
§ Muxes
§ Switches
§ Channel Banks
§ T1/E1 Test Equipment
11 of 269
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS26528.PDF ] | |
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