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EDI8L3265C fiches techniques PDF

WEDC - 64Kx32 CMOS High Speed

Numéro de référence EDI8L3265C
Description 64Kx32 CMOS High Speed
Fabricant WEDC 
Logo WEDC 





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EDI8L3265C fiche technique
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Features
64Kx32 bit CMOS Static
Random Access Memory Array
• Fast Access Times: 12*, 15, 20, and 25ns
• Individual Byte Selects
• User Configurable Organization
with Minimal Additional Logic
• Master Output Enable and Write Control
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
Surface Mount Package
• 68 Lead PLCC, No. 99 (JEDEC-M0-47AE)
• Small Footprint, 0.990 Sq. In.
• Multiple Ground Pins for Maximum
Noise Immunity
Single +5V (±5%) Supply Operation
* Advance Information
Pin Configurations and Block Diagram
EDI8L3265C
64Kx32 SRAM
64Kx32 CMOS High Speed
Static RAM
The EDI8L3265C is a high speed, high performance, four
megabit density Static RAM organized as a 64Kx32 bit
array.
Four Byte Selects, two Chip Enables, Write Control, and
Output Enable provide the user with a flexible memory
solution. The user may independently enable each of the
four bytes, and, with minimal additional peripheral logic,
the unit may be configured as a 128Kx16 array.
Fully asynchronous circuitry is used, requiring no clocks or
refreshing for operation and providing equal access and
cycle times for ease of use.
The EDI8L3265C, allows 2 megabits of memory to be
placed in less than 0.990 square inches of board space.
The EDI8L3265C can be upgraded to 128K, 256K or
512Kx32 in the same footprint using the EDI8L32128,
EDI8L32256 or the EDI8L32512C. (See page 6 for up-
grade paths).
Note: Solder Reflow temperatures should not exceed 260°C for 10 seconds.
PinNames
AØ-A15
EØ-E1
BSØ-BS3
W
G
DQØ-DQ31
VCC
VSS
NC
Address Inputs
Chip Enables (one per word)
Byte Selects (One per Byte)
Master Write Enable
Master Output Enable
Common Data Input/Output
Power (+5V±5%)
Ground
No Connection
Notes: 1. See page 6 for upgrade paths.
March 1997 Rev. 4
ECO #8302
1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

PagesPages 6
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