PDF K7R320982C Data sheet ( Hoja de datos )

Número de pieza	K7R320982C
Descripción	(K7R32xx82C) QDR II b2 SRAM
Fabricantes	Samsung semiconductor
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No Preview Available ! www.DataSheet4U.com K7R323682C K7R321882C K7R320982C 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM 36Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi- lar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.1 August 2006 1 page K7R323682C K7R321882C K7R320982C 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM PIN CONFIGURATIONS(TOP VIEW) K7R321882C(2Mx18) 123456789 A CQ NC/SA* SA W BW1 K NC R SA B NC Q9 D9 SA NC K BW0 SA NC C NC NC D10 VSS SA SA SA VSS NC D NC D11 Q10 VSS VSS VSS VSS VSS NC E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC M NC NC D16 VSS VSS VSS VSS VSS NC N NC D17 Q16 VSS SA SA SA VSS NC P NC NC Q17 SA SA C SA SA NC R TDO TCK SA SA SA C SA SA SA Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb. 2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17. PIN NAME 10 NC/SA* NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI SYMBOL K, K C, C CQ, CQ Doff SA D0-17 Q0-17 W R BW0, BW1 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC PIN NUMBERS DESCRIPTION NOTE 6B, 6A 6P, 6R Input Clock Input Clock for Output Data 1 11A, 1A Output Echo Clock 1H DLL Disable when low 3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs 10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D, 3F,2G,3J,3L,3M,2N Data Inputs 11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E, 2F,3G,3K,2L,3N,3P Data Outputs 4A 8A 7B, 5A 2H,10H Write Control Pin, active when low Read Control Pin, active when low Block Write Control Pin, active when low Input Reference Voltage 11H Output Driver Impedance Control Input 2 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply (1.8 V) 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply (1.5V or 1.8V) 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N Ground 10R JTAG Test Mode Select 11R JTAG Test Data Input 2R JTAG Test Clock 1R JTAG Test Data Output 2A,7A,10A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F, 10F,1G,9G,10G,1J,2J,9J,1K,2K,9J,1L,9L,10L,1M,2M, 9M,1N,9N,10N,1P,2P,9P No Connect 3 Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally. - 5 - Rev. 1.1 August 2006 5 Page K7R323682C K7R321882C K7R320982C 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to VSS Voltage on Input Pin Relative to VSS Storage Temperature Operating Temperature Storage Temperature Range Under Bias Commercial / Industrial SYMBOL VDD VDDQ VIN TSTG TOPR TBIAS RATING -0.5 to 2.9 -0.5 to VDD -0.5 to VDD+0.3 -65 to 150 0 to 70 / -40 to 85 -10 to 85 UNIT V V V °C °C °C *Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation. OPERATING CONDITIONS PARAMETER Supply Voltage Reference Voltage SYMBOL VDD VDDQ VREF Min 1.7 1.4 0.68 MAX 1.9 1.9 0.95 UNIT V V V DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current Output Leakage Current Operating Current (x36) Operating Current (x18) Operating Current (x9) Standby Current (NOP) Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Input Low Voltage Input High Voltage SYMBOL TEST CONDITIONS IIL VDD=Max; VIN=VSS to VDDQ IOL Output Disabled, ICC VDD=Max, IOUT=0mA Cycle Time ≥ tKHKH Min ICC VDD=Max, IOUT=0mA Cycle Time ≥ tKHKH Min. ICC VDD=Max, IOUT=0mA Cycle Time ≥ tKHKH Min. ISB1 Device deselected, IOUT=0mA, f=Max, All Inputs≤0.2V or ≥ VDD-0.2V VOH1 VOL1 VOH2 VOL2 VIL VIH IOH=-1.0mA IOL=1.0mA MIN MAX UNIT NOTES -2 +2 µA -2 +2 µA -30 - 850 -25 - 800 mA 1,5 -20 - 750 -30 - 800 -25 - 750 mA 1,5 -20 - 700 -30 - 750 -25 - 700 mA 1,5 -20 - 650 -30 - 350 -25 - 330 mA 1,6 -20 - 300 VDDQ/2-0.12 VDDQ/2+0.12 V 2,7 VDDQ/2-0.12 VDDQ/2+0.12 V 3,7 VDDQ-0.2 VDDQ V4 VSS 0.2 V 4 -0.3 VREF-0.1 V 8,9 VREF+0.1 VDDQ+0.3 V 8,10 Notes: 1. Minimum cycle. IOUT=0mA. 2. \|IOH\|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω. 3. \|IOL\|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω. 4. Minimum Impedance Mode when ZQ pin is connected to VDD. 5. Operating current is calculated with 50% read cycles and 50% write cycles. 6. Standby Current is only after all pending read and write burst operations are completed. 7. Programmable Impedance Mode. 8. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 9. VIL (Min.) DC=-0.3V, VIL (Min.) AC=-1.5V(pulse width ≤ 3ns). 10. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns). - 11 - Rev. 1.1 August 2006 11 Page

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