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PDF A64E06161 Data sheet ( Hoja de datos )
| Número de pieza | A64E06161 | |
| Descripción | 1M X 16 Bit Low Voltage Super RAM | |
| Fabricantes | AMIC Technology | |
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A64E06161
Preliminary
1M X 16 Bit Low Voltage Super RAM
Document Title
1M X 16 Bit Low Voltage Super RAM
Revision History
Rev. No.
0.0
0.1
History
Initial issue
Change VCC range and VCCQ range
Change page access time from 20ns to 25ns
Change operation current (ICC1) from 25mA to 15mA(-70)
Change operation current (ICC1) from 20mA to 12mA(-85)
Change standby current (ISB1) from 80uA to 100uA
Delete reduce memory size 16M, partial array refresh 16M
Change operation current (ICC2) form 5mA to 3mA(-70, -85)
Change PAR current 12Mb=90uA, 8Mb=80uA, 4Mb=70uA
Change TCR current +85°C=100uA +70°C=90uA
Change TCR current +45°C=85uA +15°C=75uA
Issue Date
October 12, 2003
November 30, 2004
Remark
Preliminary
PRELIMINARY (November, 2004, Version 0.1)
AMIC Technology, Corp.
1 page  
Deep Power Down Specifications and Conditions
Symbol
IZZ
Description
Deep Power-Down
Conditions
VIN = VCCQ or 0V; +25°C
ZZ = LOW
CR[4] = 0
Typ.
A64E06161
Max.
10
Units
µA
Partial Array Refresh Specifications Conditions
Symbol
Description
IPAR Partial Array Refresh
Current
Conditions
VIN = VCCQ or 0V
ZZ = LOW
CR[4] = 1
Note: IPAR (MAX) values measured with TCR set to 85°C
Density
12Mb
Array
Partition
3/4
8Mb 1/2
4Mb 1/4
Typ. Max.
90
80
70
Units
µA
µA
µA
Temperature Compensated Refresh Specifications Conditions
Symbol
ITCR
Description
Temperature
Compensated Refresh
Standby Current
Conditions
VIN = VCCQ or 0V
Chip Disabled
Density
16Mb
Max Case
Temperatures
+85°C
+70°C
+45°C
+15°C
Note: 1. ITCR (MAX) values measured with FULL ARRAY refresh.
2. This device assumes a standby mode if the chip is disabled ( CE HIGH).
Typ.
Max.
100
90
80
70
Units
µA
µA
µA
µA
Truth Table
CE ZZ OE WE LB HB I/O0 to I/O7 Mode I/O8 to I/O15 Mode
VCC Current
H H X X X X Not selected
H L X X X X Not selected
H L X X X X Not selected
Not selected
Not selected
Not selected
ISB1
IZZ*2
IPAR*2
L L X L X X Not selected
Not selected
L L Read
Read
L H L H L H Read
High - Z
H L High - Z
Read
L L Write
Write
L H X L L H Write
Not Write/Hi - Z
H
L
Not Write/Hi - Z
Write
L H H H X X High - Z
High - Z
Note: 1. X = H or L
2. DPD is enable when CR register A4 is “0”; otherwise, PAR is enable
Load CR Register
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
PRELIMINARY (November, 2004, Version 0.1)
4
AMIC Technology, Corp.
5 Page 
3. Partial Array Refresh (PAR) mode
In this mode, customers can turn off section of A64E06161 in
stand-by mode to save standby current. The A64E06161 is
divided into four 4M sections allowing certain section to be
active. The array partition to be refreshed is determined by
the respective bit in the CR register. When ZZ is active low,
only the portion of the array that is set in the CR register is
refreshed and the data is keep at a certain section of
memory. The Partial Array Refresh (PAR) mode is only
available during standby time ( ZZ low). Once ZZ is turned
A64E06161
high, the A64E06161 goes back to operating in full array
refresh. For Partial Array Refresh (PAR) mode to be
activated, the register bit, A4 must be set to a “1” value. To
change the address space of the Partial Array Refresh (PAR)
mode, the CR register must be updated using the CR
register description. If the CR register is not updated after
power on, the A64E06161 will be in its default state and the
whole memory array will be refreshed.
Partial Array Refresh – Entry/Exit
ZZ
CE or
UB / LB
1us
suspend
tCDR
Partial Array Mode/
Deep Power Down Mode
tR
Figure 2: Partial Array refresh – Entry/Exit
Partial Array Mode Timings
Parameter
tZZWE
tCDR
tR
tZZMIN
tZZCE
tZZBE
Description
ZZ LOW to WE LOW
Chip Deselect to ZZ LOW
Operation Recovery Time (Deep Power Down Mode only)
Deep Power Down Mode Time
ZZ LOW to CE LOW
ZZ LOW to UB / LD LOW
Min.
0
10
0
0
Notes:
1. OE and the data pins are in a “don’t care” state while the device is in Partial Array Mode.
2. All other timing parameters are as shown in the switching characteristics section.
3. tR applies only in the Deep Power Down Mode.
Max.
1
200
1
1
Unit
µs
µs
µs
µs
µs
µs
4. Temperature Compensated Refresh (TCR) mode
In this mode, the hidden refresh rate can be optimized for the
operating temperature. At higher temperature, the DRAM cell
must be refreshed more often than at lower temperature. By
setting the temperature of operation in CR register, the
refresh rate can be optimized to meet the low standby
current at given operating temperature. There are four
selections (+15°C, +45°C, +70°C, +85°C) in the CR register
description.
PRELIMINARY (November, 2004, Version 0.1)
10
AMIC Technology, Corp.
11 Page | ||
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