WF128K16 Datasheet PDF - ETC
| Part Number | WF128K16 | |
| Description | 5V FLASH MODULE | |
| Manufacturers | ETC | |
| Logo |  |
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WF128K16, WF256K16-XCX5
5V FLASH MODULE PRELIMINARY *
FEATURES
s Access Times of 50, 60, 70, 90, 120 and 150ns
s 40 pin Ceramic DIP (Package 303)
s Organized as 128Kx16 and 256Kx16
s Sector Architecture
• 8 equal size sectors of 16KBytes each per chip
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
s 100,000 Erase/Program Cycles Minimum (0°C to 70°C)
s Data Retention, 10 Years at 125°C
s Commercial, Industrial and Military Temperature Ranges
s 5 Volt Programming; 5V ±10% Supply
s Low Power CMOS
s Embedded Erase and Program Algorithms
s TTL Compatible Inputs and CMOS Outputs
s Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s Page Program Operation and Internal Program Control Time
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note: Programming information available upon request.
FIG. 1 PIN CONFIGURATION AND BLOCK DIAGRAM
TOP VIEW
CS2*/NC
CS1
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
GND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 WE
38 A16
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 GND
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
* CS2 for 256Kx16 and NC for 128Kx16
BLOCK DIAGRAM
FOR WF128K16-XCX5
WE
OE
A0-16
PIN DESCRIPTION
A0-16
I/O0-15
CS1-2
OE
WE
VCC
GND
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
BLOCK DIAGRAM
FOR WF256K16-XCX5
I/O0-7
I/O8-15
WE
OE
A0-16
I/O0-7
I/O8-15
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
CS1
C S 1(1)
C S 2(1)
NOTE:
1. CS1 and CS2 are used to select the lower and upper 128Kx16 of the
device. CS1 and CS2 must not be enabled at the same time.
7
October 1998
1 White Microelectronics • Phoenix, AZ • (602) 437-1520
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WF128K16, WF256K16-XCX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Write Cycle Time
WE Setup Time
CS Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
WE Hold from WE High
CS Pulse Width High
Duration of Programming Operation
Duration of Erase Operation
Read Recovery before Write
Chip Programming Time
Symbol
tAVAV tWC
tWLEL tWS
tELEH tCP
tAVEL tAS
tDVEH tDS
tEHDX tDH
tELAX tAH
tEHWH tWH
tEHEL tCPH
tWHWH1
tWHWH2
tGHEL
-50
Min Max
50
-60
Min Max
60
-70 -90
Min Max Min Max
70 90
-120
Min Max
120
0 000 0
25 30 35 45 50
0 000 0
25 30 30 45 50
0 000 0
40 45 45 45 50
0 000 0
20 20 20 20 20
14 14 14 14 14
2.2 60 2.2 60 2.2 60 2.2 60 2.2 60
0 000 0
12.5 12.5
12.5 12.5 12.5
-150
Min Max
150
Unit
ns
0 ns
50 ns
0 ns
50 ns
0 ns
50 ns
0 ns
20 ns
14 µs
2.2 60 sec
0 ns
12.5 sec
FIG. 2
AC TEST CIRCUIT
Current Source
D.U.T.
Ceff = 50 pf
Current Source
I OL
I OH
7
VZ ≈ 1.5V
(Bipolar Supply)
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
VIL = 0, VIH = 3.0
5
1.5
1.5
Unit
V
ns
V
V
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
5 White Microelectronics • Phoenix, AZ • (602) 437-1520
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| Information | Total 11 Pages | |
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