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White Electronic - Synchronous Pipeline Burst NBL SRAM

Numéro de référence WED2ZL361MS
Description Synchronous Pipeline Burst NBL SRAM
Fabricant White Electronic 
Logo White Electronic 





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WED2ZL361MS fiche technique
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White Electronic Designs
WED2ZL361MS
1Mx36 Synchronous Pipeline Burst NBL SRAM
FEATURES
Fast clock speed: 250, 225, 200, 166, 150,
133MHz
Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns
Fast OE# access times: 2.6, 2.8, 3.0, 3.5, 3.8,
4.2ns
Separate +2.5V ± 5% power supplies for Core, I/O
(VCC, VCCQ)
Snooze Mode for reduced-standby power
Individual Byte Write control
Clock-controlled and registered addresses, data
I/Os and control signals
Burst control (interleaved or linear burst)
Packaging:
119-bump BGA package
Low capacitive bus loading
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed,
low-power CMOS designs that are fabricated using an
advanced CMOS process. WEDC’s 32Mb SyncBurst
SRAMs integrate two 1M x 18 SRAMs into a single BGA
package to provide 1M x 36 configuration. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single-clock input (CK). The NBL or No
Bus Latency Memory utilizes all the bandwidth in any
combination of operating cycles. Address, data inputs, and
all control signals except output enable and linear burst
order are synchronized to input clock. Burst order control
must be tied “High or Low.” Asynchronous inputs include the
sleep mode enable (ZZ). Output Enable controls the outputs
at any given time. Write cycles are internally self-timed and
initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation and
provides increased timing flexibility for incoming signals.
NOTE: NBL (No Bus Latency) is equivalent to ZBT™
PIN CONFIGURATION
(TOP VIEW)
12 3 4 5 67
A VCCQ SA SA SA SA SA VCCQ
B SA CE2 SA ADV# SA CE2# NC
C NC SA SA VCC SA SA NC
D DQc DQPc VSS NC VSS DQPb DQb
E DQc DQc VSS CE1# VSS DQb DQb
F VCCQ DQc VSS OE# VSS DQb VCCQ
G DQc DQc BWc# SA BWb# DQb DQb
H DQc DQc VSS WE# VSS DQb DQb
J VCCQ VCC NC VCC NC VCC VCCQ
K DQd DQd VSS CK VSS DQa DQa
L DQd DQd BWd# NC BWa# DQa DQa
M VCCQ DQd VSS CKE# VSS DQa VCCQ
N DQd DQd VSS SA1 VSS DQa DQa
P DQd DQPd VSS SA0 VSS DQPa DQa
R NC SA LBO# VCC NC SA NC
T NC NC SA SA SA NC ZZ
U VCCQ NC NC NC NC NC VCCQ
BLOCK DIAGRAM
CK
CKE#
ADV#
LBO#
CE1#
CE2
CE2#
OE#
WE#
ZZ
1M x 18
CK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ
1M x 18
CK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ
Address Bus
(SA0 - SA19)
DQc, DQd
DQPc, DQPd
DQa, DQb
DQPa, DQPb
DQa - DQd
DQPa - DQPd
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct, 2002
Rev. 5
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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