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PDF EDI8L24129V Data sheet ( Hoja de datos )

Número de pieza EDI8L24129V
Descripción 128Kx24 SRAM 3.3 Volt
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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White Electronic Designs
EDI8L24129V
128Kx24 SRAM 3.3 Volt
FEATURES
128Kx24 bit CMOS Static
Random Access Memory Array
• Fast Access Times: 10, 12, and 15ns
• Master Output Enable and Write Control
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
Surface Mount Package
• 119 Lead BGA (JEDEC MO-163), No. 391
• Small Footprint, 14mm x 22mm
• Multiple Ground Pins for Maximum
Noise Immunity
Single +3.3V (±5%) Supply Operation
DSP Memory Solution
Motorola DSP5630xTM
Analog Devices SHARCTM
DESCRIPTION
The EDI8L24129VxxBC is a 3.3V, three megabit SRAM
constructed with three 128Kx8 die mounted on a multi-
layer laminate substrate. With 10 to 15ns access times,
x24 width and a 3.3V operating voltage, the EDI8L24129V
is ideal for creating a single chip memory solution for the
Motorola DSP5630x (Figure 3) or a two chip solution for
the Analog Devices SHARCTM DSP (Figure 4).
The single or dual chip memory solutions offer improved
system performance by reducing the length of board traces
and the number of board connections compared to using
multiple monolithic devices. For example, the capacitance
load on the data lines for the BGA package is 58% less
than a monolithic SOJ solution.
The JEDEC Standard 119 lead BGA provides a 44% space
savings over using 128Kx8, 300mil wide SOJs and the BGA
package has a maximum height of 100 mils compared to
148 mils for the SOJ packages. The BGA package also
allows the use of the same manufacturing and inspection
techniques as the Motorola DSP, which is also in a BGA
package.
PIN CONFIGURATION
1 2 3 4 5 67
A NC AO A1 A2 A3 A4 NC
B NC A5 A6 E# A7 A8 NC
C I/012 NC NC NC NC NC I/00
D I/013 VCC GND GND GND VCC I/01
E I/014 GND VCC GND VCC GND I/02
F I/015 VCC GND GND GND VCC I/03
G I/016 GND VCC GND VCC GND I/04
H I/017 VCC GND GND GND VCC I/05
I NC GND VCC GND VCC GND NC
J I/018 VCC GND GND GND VCC I/06
K I/019 GND VCC GND VCC GND I/07
L I/020 VCC GND GND GND VCC I/08
M I/021 GND VCC GND VCC GND I/09
N I/022 VCC GND GND GND VCC I/010
O I/023 NC NC NC NC NC I/011
P NC A9 A10 W# A11 A12 NC
Q NC A13 A14 G# A15 A16 NC
PIN NAMES
AØ-A16 Address Inputs
E# Chip Enable
W# Master Write Enable
G# Master Output Enable
DQØ-DQ23 Common Data Input/Output
VCC Power (3.3V±5%)
GND Ground
NC No Connection
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 5
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




EDI8L24129V pdf
White Electronic Designs
EDI8L24129V
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
Note 1: Parameter guaranteed, but not tested.
AC CHARACTERISTICS – WRITE CYCLE
Symbol
JEDEC
tAVAV
tELWH
tELEH
tAVWL
tAVEL
tAVWH
tAVEH
tWLWH
tWLEH
tWHAX
tEHAX
tWHDX
tEHDX
tWLQZ
tDVWH
tDVEH
tWHQX
Alt.
tWC
tCW
tCW
tAS
tAS
tAW
tAW
tWP
tWP
tWR
tWR
tDH
tDH
tWHZ
tDW
tDW
tWLZ
10ns
Min Max
10
8
8
0
0
8
8
8
8
0
0
0
0
05
6
6
3
12ns
Min Max
12
9
9
0
0
9
9
10
10
0
0
0
0
06
6
6
3
15ns
Min Max
15
9
9
0
0
10
10
11
11
0
0
0
0
07
7
7
3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE – W# CONTROLLED
tAVAV
A
E#
W#
D
Q
tAVWL
tELWH
tAVWH
tWLWH
tWHAX
tWLQZ
tDVWH
tWHDX
DATA VALID
tWHQX
HIGH Z
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 5
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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