PDF EDI2CG272128V Data sheet ( Hoja de datos )

Número de pieza	EDI2CG272128V
Descripción	Sync/Sync Burst SRAM SO-DIMM
Fabricantes	White Electronic
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No Preview Available ! www.DataSheet4U.com White Electronic Designs EDI2CG272128V ADVANCED* 2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM FEATURES 2x128Kx72 Synchronous, Synchronous Burst Flow-Through Architecture Linear and Sequential Burst Support via MODE pin Access Speed(s): TKHQV = 8.5, 9, 12, 15ns Clock Controlled Registered Bank Enables (E1#, E2#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Aysnchronous Output Enable (G#) Internally Self-timed Write Individual Bank Sleep Mode enables (ZZ1, ZZ2) Gold Lead Finish 3.3V ± 10% Operation Common Data I/O High Capacitance (30pf) drive, at rated Access Speed Single Total Array Clock Multiple Vcc and Gnd DESCRIPTION The EDI2CG272128VxxD1 is a Synchronous/Synchronous Burst SRAM, 72 position DIMM (144 contacts) Module, small outline. The Module contains four (4) Synchronous Burst Ram Devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is deﬁned as a Sync/ Sync Burst, Flow-Through, with support for linear burst. This module provides High Performance, 2-1-1-1 accesses when used in Burst Mode, and used as a Synchronous Only Mode, provides a high performance cost advantage over BiCMOS aysnchronous device architectures. Synchronous Only operations are performed via strapping ADSC# Low, and ADSP# / ADV# High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes. Synchronous/Synchronous Burst operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output enable. This Module has been deﬁned for Quad Words in both Read and Write Operations. *This product is under development, is not qualiﬁed or characterized and is subject to change or cancellation without notice. White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. August 2000 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs EDI2CG272128V ADVANCED SYNCHRONOUS BURST - TRUTH TABLE Operation Deselected Cycle, Power Down; Bank 1 Deselected Cycle, Power Down; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 2 Write Cycle, Begin Burst; Bank 1 Write Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 2 E1# E2# ADSP# ADSC# ADV# GW# G# HX X L X XX XH X L X XX LH L X XXL LH L X X XH HL L X XXL HL L X X XH LH H L X LX HL H L X LX LH H L XHL LH H L X HH HL H L XHL HL H L X HH XH X H L HL XH X H L HH HX X H L HL HX X H L HH HH X H L HL HH X H L HH HH X H L HL HH X H L HH XH H H L LX HH X H L LX HX H H L LX HH X H L LX XH H H H HL XH H H H HH HX H H H HL HX H H H HH HH X H HHL HH X H H HH HH X H HHL HH X H H HH XH H H H LX HH X H H LX HX H H H LX HH X H H LX CK DQ Addr. Used L-H High-Z None L-H High-Z None L-H Q External L-H High-Z External L-H Q External L-H High-Z External L-H D External L-H D External L-H Q External L-H High-Z External L-H Q External L-H High-Z External L-H Q Next L-H High-Z Next L-H Q Next L-H High-Z Next L-H Q Next L-H High-Z Next L-H Q Next L-H High-Z Next L-H D Next L-H D Next L-H D Next L-H D Next L-H Q Current L-H High-Z Current L-H Q Current L-H High-Z Current L-H Q Current L-H High-Z Current L-H Q Current L-H High-Z Current L-H D Current L-H D Current L-H D Current L-H D Current White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. August 2000 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 5 Page White Electronic Designs EDI2CG272128V ADVANCED FIG. 7 SYNCHRONOUS (NON-BURST) READ/WRITE CYCLE tKHKH tKHKL tKLKH CK tAVKH Ex# ADDR G# GW# DQ Addr 1 tKHQV Addr 2 tKHDX tKHQX Q (Addr 1) D (Addr 2) tDVKH Read Cycle Write Cycle Back to Back Cycles G# Controlled tKHDX White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. August 2000 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 11 Page

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