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PDF IDT70T16 Data sheet ( Hoja de datos )
| Número de pieza | IDT70T16 | |
| Descripción | (IDT70T15 / IDT70T16) HIGH-SPEED 2.5V 16/8K X 9 DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
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HIGH-SPEED 2.5V
16/8K X 9 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70T16/5L
.eatures
x True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x High-speed access
– Commercial:20/25ns (max.)
– Industrial: 25ns (max.)
x Low-power operation
– IDT70T16/5L
Active: 200mW (typ.)
Standby: 600µW (typ.)
x IDT70T16/5 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
x M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
x Busy and Interrupt Flag
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x LVTTL-compatible, single 2.5V (±100mV) power supply
x Available in an 80-pin TQFP and 100-pin fpBGA
x Industrial temperature range (–40°C to +85°C) is available
for selected speeds
.unctional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O8L
BUSYL(2,3)
A13L(1)
A0L
I/O
Control
I/O
Control
Address
Decoder
14
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
14
SEML
INTL(3)
NOTES:
1. A13 is a NC for IDT70T15.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
M/S
Address
Decoder
CER
OER
R/WR
I/O0R-I/O8R
BUSYR(2,3)
A13R(1)
A0R
SEMR
INTR(3)
5663 drw 01
©2002 Integrated Device Technology, Inc.
1
AUGUST 2002
DSC 5663/1
1 page  
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
S ym bol
Ratin g
Com m ercial
& Industrial
Unit
V TERM(2 )
Te rm in al V o ltag e
w ith R e s p e c t to G N D
-0.5 to + 3.6
V
TBIAS(3 )
Te m p e ra tu re U n d e r B ia s -55 to + 1 25
oC
TSTG
S to ra g e Te m p e ra ture
-65 to + 150
oC
TJN
J u n c tio n Te m p e rature
+ 150
oC
IOUT D C O u tp u t C urre nt
50 mA
NOTES:
5 6 63 tb l 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VTERM must not exceed VDD+ 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
Capacitance(1)(TA = +25°C, f = 1.0MHz)
Sym bol
Param eter
Conditions(2) M ax. Unit
CIN Inp ut Cap acitanc e
V IN = 3d V
9 pF
CO UT Outp ut Cap ac itance
VOUT = 3dV
10 pF
NOTES:
5663 tbl 07
1. This parameter is determined by device characteristics but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V .
Maximum Operating
Temperature and Supply Voltage(1)
Grade
Am b ien t
T em p erature
GND
V DD
Com merc ial
0OC to + 70OC
0V 2.5V + 100mV
Ind ustrial
-40OC to + 85OC 0V 2.5V + 100m V
NOTES:
5663 tbl 05
1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating
Conditions
Symbol
Param eter
M in. Typ.
M ax.
Un it
V DD S up p ly Vo ltag e
2.4 2.5 2.6 V
V S S G ro un d
00
0V
V IH In p u t H ig h Vo lta g e
1 . 7 ____ V D D+ 0 . 3 (2 ) V
V IL In p u t L o w V o lta g e
-0 .3 (1 )
____
0.7
V
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
5 6 63 tb l 06
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
Sym bol
|ILI|
|ILO |
VOL
V OH
P aram eter
Inp ut Le ak ag e C urre nt(1)
O utp ut L e ak ag e C urre nt
O utp ut L o w Vo ltag e
O utp ut H ig h Vo ltag e
NOTE:
1. At VDD < 2.0V, Input leakages are undefined.
Test Conditions
V DD = 2.6V, V IN = 0V to V DD
CE = V IH , V O UT = 0V to V DD
IO L = + 2m A
IOH = -2m A
70T16/5L
Min.
M a x.
___ 5
___ 5
___ 0. 4
2.0
___
Unit
µA
µA
V
V
5663 tb l 08
6.452
5 Page 
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70T16/5L20
Com 'l Only
70T16/5L25
Com 'l
& Ind
S ym b o l
BUSY TIM ING (M /S = VIH)
Param eter
Min.
M ax.
Min.
M ax.
Unit
tBAA BUSY A cc e ss Tim e fro m A d d re s s M atch
____ 20 ____ 20 ns
tBDA BUSY Di s ab le Tim e fro m A d d re s s No t M atche d
____ 20 ____ 20 ns
tBAC BUSY A c ce ss Tim e fro m Chip E nab le LOW
____ 20 ____ 20 ns
tBDC BUSY Dis ab le Tim e fro m Chip E nab le HIGH
____ 17 ____ 17 ns
tAPS A rb itratio n P rio rity S e t-up Tim e (2)
5 ____ 5 ____ ns
tBDD BUSY Disab le to Valid Data(3)
tWH W rite Ho ld A fte r BUSY(5)
BUSY TIM ING (M /S = VIL)
____ 30 ____ 30 ns
15 ____ 17 ____ ns
tWB BUSY Inp ut to W rite (4)
tWH W rite Ho ld A fte r BUSY(5)
0 ____ 0 ____ ns
15 ____ 17 ____ ns
PORT-TO-PORT DELAY TIM ING
tWDD W r ite P uls e to D ata De lay(1)
tDDD W rite Data Va lid to Re ad D ata De lay (1)
____ 45 ____ 50 ns
____ 35 ____ 35 ns
NOTES:
5663 tb l 1 3
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
tWC
ADDR"A"
MATCH
R/W"A"
tWP
DATAIN "A"
ADDR"B"
BUSY"B"
tAPS (1)
tDW
VALID
MATCH
tDH
tBDA
tBDD
tWDD
DATAOUT "B"
NOTES:
tDDD (3)
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL.
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
VALID
5663 drw 11
6.1412
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet IDT70T16.PDF ] | |
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