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PDF FCA20N60 Data sheet ( Hoja de datos )

Número de pieza FCA20N60
Descripción N-Channel MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FCA20N60 Hoja de datos, Descripción, Manual

August 2014
FCA20N60
N-Channel SuperFET® MOSFET
600 V, 20 A, 190 mΩ
Features
• 650V @ TJ = 150°C
• Typ. RDS(on) = 150 mΩ
• Ultra Low Gate Charge (Typ. Qg = 75 nC )
• Low Effective Output Capacitance (Typ. Coss(eff.) = 165 pF )
• 100% Avalanche Tested
Applications
• Solar Inverter
• AC-DC Power Supply
Description
SuperFET® MOSFET is Fairchild Semiconductor’s first genera-
tion of high voltage super-junction (SJ) MOSFET family that is
utilizing charge balance technology for outstanding low on-
resistance and lower gate charge performance. This technology
is tailored to minimize conduction loss, provide superior switch-
ing performance, dv/dt rate and higher avalanche energy. Con-
sequently, SuperFET MOSFET is very suitable for the switching
power applications such as PFC, server/telecom power, FPD
TV power, ATX power and industrial power applications.
D
G
D
S
TO-3PN
G
MOSFET Maximum Ratings TC = 25oC unless otherwise noted.
S
Symbol
VDSS
VGSS
ID
IDM
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain to Source Voltage
Gate-Soure voltage
Drain Current
Drain Current
- Continuous (TC = 25oC)
- Continuous (TC = 100oC)
- Pulsed
(Note 1)
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
Power Dissipation
(TC = 25oC)
- Derate Above 25oC
(Note 3)
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds
Thermal Characteristics
Symbol
RθJC
RθJA
Parameter
Thermal Resistance, Junction to Case, Max.
Thermal Resistance, Junction to Ambient, Max.
FCA20N60 /
FCA20N60_F109
600
±30
20
12.5
60
690
20
20.8
4.5
208
1.67
-55 to +150
300
FCA20N60 /
FCA20N60_F109
0.6
41.7
Unit
V
V
A
A
mJ
A
mJ
V/ns
W
W/oC
oC
oC
Unit
oC/W
©2008 Fairchild Semiconductor Corporation
FCA20N60 Rev. C0
1
www.fairchildsemi.com

1 page




FCA20N60 pdf
IG = const.
Figure 12. Gate Charge Test Circuit & Waveform
V10GVS
VDS
VGS
RG
RL
VDD
VDS
90%
DUT
VGS 10%
td(on)
tr
t on
Figure 13. Resistive Switching Test Circuit & Waveforms
td(off)
tf
t off
V1G0GVSS
tp
VDS
ID
RG
L
EAS = --21-- L IAS2
------B--V--D--S-S-------
BVDSS - VDD
BVDSS
IAS
VDD ID (t)
DUT
VDD
VDS (t)
t p Time
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
©2008 Fairchild Semiconductor Corporation
FCA20N60 Rev. C0
5
www.fairchildsemi.com

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