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PDF UPD44324362 Data sheet ( Hoja de datos )
| Número de pieza | UPD44324362 | |
| Descripción | (UPD44324xx2) 36M-BIT DDRII SRAM 2-WORD BURST OPERATION | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44324082, 44324092, 44324182, 44324362
36M-BIT DDRII SRAM
2-WORD BURST OPERATION
Description
The µPD44324082 is a 4,194,304-word by 8-bit, the µPD44324092 is a 4,194,304-word by 9-bit, the µPD44324182 is a
2,097,152-word by 18-bit and the µPD44324362 is a 1,048,576-word by 36-bit synchronous double data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The µPD44324082, µPD44324092, µPD44324182 and µPD44324362 integrate unique synchronous peripheral circuitry
and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K
and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA package (13 x 15)
• HSTL Interface
• DLL circuitry for wide output data valid window and future frequency scaling
• Pipelined double data rate operation
• Common data input/output bus
• Two-tick burst for low DDR transaction size
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
• User programmable impedance output
<R> • Fast clock cycle time : 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
• Simple control logic for easy depth expansion
• JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16780EJ3V0DS00 (3rd edition)
Date Published March 2006 NS CP(K)
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2003
1 page  
µPD44324082, 44324092, 44324182, 44324362
165-pin PLASTIC BGA (13 x 15)
(Top View)
[µPD44324182F5-EQ2]
[µPD44324182F5-EQ2-A]
1 2 3 4 5 6 7 8 9 10 11
A CQ#
VSS
A R, W# BW1# K#
NC LD#
A
A CQ
B NC DQ9 NC A NC K BW0# A NC NC DQ8
C NC NC NC VSS A A0 A VSS NC DQ7 NC
D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6
F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5
G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC
H DLL# VREF VDDQ VDDQ
VDD
VSS
VDD
VDDQ VDDQ
VREF
ZQ
J NC
NC
NC VDDQ VDD
VSS
VDD VDDQ NC
DQ4
NC
K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3
L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2
M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC
N NC
NC DQ16 VSS
A
A
A VSS NC NC NC
P NC
NC DQ17 A
A
C
A
A NC NC DQ0
R TDO TCK
A
A
A C# A
A
A TMS TDI
A0, A
DQ0 to DQ17
LD#
R, W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1. Refer to Package Drawing for the index mark.
2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.
2A of this product can also be used as NC.
Data Sheet M16780EJ3V0DS
5
5 Page 
µPD44324082, 44324092, 44324182, 44324362
2. Clock starts before VDD/VDDQ stable
The clock is supplied from a clock generator.
(a)
VDD/VDDQ
VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)
DLL#
Fix high (or tied to VDDQ)
Clock
Unstable Clock
(level, frequency)
Clock Start
30 ns. (MIN.)
Clock Stop
1,024 cycles or more
Stable Clock
Normal Operation Start
(b)
VDD/VDDQ
DLL#
Clock
High or low
VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)
30 ns (MIN.)
DLL# low
Switched to high after Clock is stable.
Unstable Clock
(level, frequency)
Clock Start
Clock keep running
1,024 cycles or more Normal
Stable Clock
Operation
Start
Data Sheet M16780EJ3V0DS
11
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet UPD44324362.PDF ] | |
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