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PDF EDI7F292MC Data sheet ( Hoja de datos )
| Número de pieza | EDI7F292MC | |
| Descripción | (EDI7F292MC / EDI7F492MC) Boot-Only Sector Erase Flash Memory | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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White Electronic Designs
EDI7F292MC
EDI7F492MC
PRELIMINARY*
4MB/8MB (2x2Mx8 / 4x2Mx8) Flash Module 5.0V, Boot-Only
Sector Erase Flash Memory
ARCHITECHTURE
FEATURES
5.0 Volt ± 10% fir read and write operations
• Minimizes system level power requirements
Compatible with JEDEC-standards
• Pinout and software compatible with single-power
supply Flash
• Superior inadvertent write protection
80 SIMM (JEDEC)
Minimum 100,000 write/erase cycles guaranteed
High performance
• 70 ns maximum access time
Sector erase architecture
• Uniform sectors of 64 Kbytes each
• Any combination of sectors can be erased. Also
supports full chip erase
Group sector protection
• Hardware method that disables any combination
of sector groups from write or erase operations
(a sector group consists of 4 adjacent sectors of
64Kbytes each)
Embedded Erase Algorithms
• Automatically pre-programs and erases the chip
or any sector
Embedded Program Algorithms
• Automatically programs and verifies data at
specified address
Data# Polling and Toggle Bit feature for detection
of program or erase cycle completion
Ready/Busy# output (RY/BY#)
• Hardware method for detection of program or
erase cycle completion
Erase Suspend/Resume
• Supports reading or programming data to a
sector not being erased
Low power consumption (EDI7292MC)
• 50 mA typical active read current
• 60 mA typical program/erase current
Low power consumption (EDI7492MC)
• 100 mA typical active read current
• 120 mA typical program/erase current
Enhanced power management for standby mode
• <1 µA typical standby current
• Standard access time from standby mode
Hardware RESET# pin
• Resets internal state machine to the read mode
* This product is under development, is not qualified or characterized and is subject to
change without notice.
DESCRIPTION
The EDI7F292/492MC is a 32/64 Mbit, 5.0 Volt-only
Flash memory organized as 2 Megabytes of 8 bits each.
The 2Mbytes of data is divided into 32 sectors of 64
Kbytes for flexible erase capability. The 8 bits of data
appear on DQ0–DQ7. The EDI7F292/492MC is offered
in 80 Pin SIMM packages. This device is designed to be
programmed in-system with the standard system 5.0 Volt
VCC supply. 12.0 Volt VPP is not required for program or
erase operations. The device can also be reprogrammed
in standard EPROM programmers.
The standard EDI7F292/492MC offers access times of 100
ns, and 120 ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention,
the device has separate chip enable 4 CS#, write enable
WE#, and output enable OE# controls.
The EDI7F292/492MC is entirely command set compatible
with the JEDEC single-power supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from 12.0 Volt Flash or
EPROM devices.
The EDI7F292/492MC is programmed by executing
the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal
algorithm that automatically times the program pulse widths
and verifies proper cell margin. Erase is accomplished by
January 2006
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
EDI7F292MC
EDI7F492MC
PRELIMINARY
AUTOSELECT
The autoselect mode allows the reading of a binary code
from the device and will identify its manufacturer and
type. This mode is intended for use by programming
equipment for the purpose of automatically matching
the device to be programmed with its corresponding
programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must
force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the device
outputs by toggling address A0 from VIL to VIH All addresses
are don’t cares except A0, A1, and A6 (seeTable 2).
The manufacturer and device codes may also be
read via the command register, for instances when
the EDI7F292/492MC is erased or programmed in a
system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 5 (see Autoselect
Command Sequence).
Byte 0 (A0 = VIL) ) represents the manufacturer’s code
(WEDC = 01h) and byte 1 (A0 = VIH) the device identifier
code for EDI7F292/492MC = ADh. These two bytes are
given in the table below. All identifiers for manufacturer
and device will exhibit odd parity with DQ7 defined as the
parity bit. In order to read the proper device codes when
executing the Autoselect, A1 must be VIL (see Table 2).
The autoselect mode also facilitates the determination
of sector group protection in the system. By performing
a read operation at the address location XX02h with the
higher order address bits A18, A19, and A20 set to the
desired sector group address, the device will return 01h
for a protected sector group and 00h for a non-protected
sector group.
TABLE 2. EDI7F292/492MC SECTOR PROTECTION VERIFY AUTOSELECT CODES
Type
A18 to A20
A6
A1
A0
Code
(HEX)
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacture Code-WEDC
EDI7F292/492MC Devis
Sector Group Protection
X X X VIL VIL VIL 01H 0 0 0 0 0 0 0 1
X X X VIL VIL VIH ADH 1 0 1 0 1 1 0 1
Sector Group
Address
VIL VIH VIL 01H* 0 0 0 0 0 0 0 1
* Outputs 01H at protected sector addresses
January 2006
Rev. 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
EDI7F292MC
EDI7F492MC
PRELIMINARY
TABLE 6. WRITE OPERATION STATUS
Status
DQ7 CQ6 DQ5 DQ3 DQ2
Byte Program in Embedded Program Algorithm
DQ7#
Toggle
0
0
1
Embedded Program Algorithm
0 Toggle 0
1 Toggle
In Progress
Erase Suspended Read
1 1 0 1 Toggle
(Erase Suspended Sector)
(Note 1)
Erase Suspended Mode
Erase Suspended Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspended Read
(Non-Erase Suspended Sector)
DQ7#
Toggle
(Note 2)
0
11
(Note 3)
Exceeded Time Byte Program in Embedded Program Algorithm
Limits
Program/Erase Program in Embedded Program Algorithm
DQ7#
0
Toggle
Toggle
1
1
01
1 N/A
Erase Suspended Mode
Erase Suspended Read
(Non-Erase Suspended Sector)
DQ7#
Toggle
1
1 N/A
Notes:
1. Performing successive read operations from the erase-suspended sector will cause DQ2 to toggle.
2. Performing successive read operations from any address will cause DQ6 to toggle.
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic ‘1’ at the DQ2 bit.
However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
DQ7
DATA# POLLING
The EDI7F292/492MC device features Data# Polling
as a method to indicate to the host that the embedded
algorithms are in progress or completed. During the
Embedded Program Algorithm, an attempt to read the
device will produce the complement of the data last written
to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the
true data last written to DQ7. During the Embedded Erase
Algorithm, an attempt to read the device will produce a
“0” at the DQ7 output. Upon completion of the Embedded
Erase Algorithm an attempt to read the device will produce
a “1” at the DQ7 output. The flowchart for Data# Polling
(DQ7) is shown in Figure 3.
Data# Polling will also flag the entry into Erase Suspend.
DQ7 will switch “0” to “1” at the start of the Erase Suspend
mode. Please note that the address of an erasing sector
must be applied in order to observe DQ7 in the Erase
Suspend Mode.
During Program in Erase Suspend, Data# Polling will
perform the same as in regular program execution outside
of the suspend mode.
sequence. For sector erase, the Data# Polling is valid after
the last rising edge of the sector erase WE# pulse. Data#
Polling must be performed at sector addresses within any
of the sectors being erased and not a sector that is within
a protected sector group. Otherwise, the status may not
be valid.
Just prior to the completion of Embedded Algorithm
operations DQ7 may change asynchronously while the
output enable (OE#) is asserted low. This means that the
device is driving status information on DQ7 at one instant
of time and then that byte’s valid data at the next instant
of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the
device has completed the Embedded Algorithm operations
and DQ7 has a valid data, the data outputs on DQ0–DQ6
may be still invalid. The valid data on DQ0–DQ7 can be
read on the successive read attempts.
The Data# Polling feature is only active during the
Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, erase-suspend-program mode,
or sector erase time-out (see Table 6).
For chip erase, the Data# Polling is valid after the
rising edge of the sixth WE# pulse in the six write pulse
See Figure 11 for the Data# Polling timing specifications
and diagrams.
January 2006
Rev. 1
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EDI7F292MC.PDF ] | |
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