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PDF AD9397 Data sheet ( Hoja de datos )
| Número de pieza | AD9397 | |
| Descripción | DVI Display Interface | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9397 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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FEATURES
DVI interface
Supports high-bandwidth digital content protection
RGB to YCbCr 2-way color conversion
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Digital video interface
DVI 1.0
150 MHz DVI receiver
Supports high-bandwidth digital content protection
(HDCP 1.1)
APPLICATIONS
Advanced TVs
HDTVs
Projectors
LCD monitors
GENERAL DESCRIPTION
The AD9397 is a digital visual interface (DVI) receiver
integrated on a single chip. Also included is support for high
bandwidth digital content protection (HDCP) with internal key
storage.
The AD9397 contains a DVI 1.0-compatible receiver and
supports all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 × 1024 @ 80 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can receive encrypted
DVI Display Interface
AD9397
FUNCTIONAL BLOCK DIAGRAM
SCL
SDA
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
DDCSCL
DDCSDA
MCL
MDA
SERIAL REGISTER
AND
POWER MANAGEMENT
DIGITAL INTERFACE
R/G/B 8 × 3
OR YCbCr
DVI RECEIVER
2 DATACK
DE
HSYNC
VSYNC
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2 DATACK
HSOUT
VSOUT
SOGOUT
DE
HDCP
AD9397
Figure 1.
video content. The AD9397 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and
renewability of that authentication during transmission as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9397 is
provided in a space-saving, 100-lead, surface-mount, Pb-free
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD9397
Parameter
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew
(TDPS)
Channel to Channel Differential Input
Skew (TCCS)
Low-to-High Transition Time for Data
and Controls (DLHT)
Test
Level
IV
IV
IV
IV
Low-to-High Transition Time for DATACK
(DLHT)
IV
IV
High-to-Low Transition Time for Data
and Controls (DHLT)
IV
IV
High-to-Low Transition Time for DATACK
(DHLT)
IV
IV
Clock to Data Skew5 (TSKEW)
Duty Cycle, DATACK5
DATACK Frequency (FCIP)
IV
IV
VI
Conditions
AD9397KSTZ-100
AD9397KSTZ-150
Min Typ Max Min Typ Max Unit
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
Output drive = high;
CL = 10 pF
Output drive = low;
CL = 5 pF
−0.5
45
20
+2.0 −0.5
50
360 ps
6 Clock
Period
900 ps
1300 ps
650 ps
1200 ps
850 ps
1250 ps
800 ps
1200 ps
+2.0 ns
55 %
150 MHz
1 The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.
2 The typical pattern contains a gray scale area, output drive = high.
3 Specified current and power values with a worst-case pattern (on/off).
4 DATACK load = 10 pF, data load = 5 pF.
5 Drive strength = high.
Rev. 0 | Page 5 of 28
5 Page 
TIMING
The output data clock signal is created so that its rising edge
always occurs between data transitions and can be used to latch
the output data externally.
Figure 3 shows the timing operation of the AD9397.
tPER
DATACK
tDCYCLE
tSKEW
DATA
HSOUT
Figure 3. Output Timing
HSYNC TIMING
Horizontal sync (HSYNC) is processed in the AD9397 to
eliminate ambiguity in the timing of the leading edge with
respect to the phase-delayed pixel clock and data.
The HSYNC input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with
respect to HSYNC, through a full 360° in 32 steps via the phase
adjust register (to optimize the pixel sampling time). Display
systems use HSYNC to align memory and display write cycles,
so it is important to have a stable timing relationship between
the HSYNC output (HSOUT) and data clock (DATACK).
VSYNC FILTER AND ODD/EVEN FIELDS
The VSYNC filter is used to eliminate spurious VSYNCs,
maintain a consistent timing relationship between the VSYNC
and HSYNC output signals, and generate the odd/even field
output.
The filter works by examining the placement of VSYNC
with respect to HSYNC and, if necessary, slightly shifting
it in time at the VSOUT output. The goal is to keep the
VSYNC and HSYNC leading edges from switching at the
same time, eliminating confusion as to when the first line
of a frame occurs. Enabling the VSYNC filter is done with
Register 0x21[5]. Use of the VSYNC filter is recommended for
all cases, including interlaced video, and is required when using
the HSYNC per VSYNC counter. Figure 4 and Figure 5
illustrate even/odd field determination in two situations.
AD9397
SYNC SEPARATOR THRESHOLD
QUADRANT
HSIN
VSIN
FIELD 1
23
FIELD 0
41
FIELD 1
23
VSOUT
O/E FIELD
EVEN FIELD
Figure 4. VSYNC Filter
FIELD 0
41
SYNC SEPARATOR THRESHOLD
QUADRANT
HSIN
VSIN
FIELD 1
23
FIELD 0
41
FIELD 1
23
FIELD 0
41
VSOUT
O/E FIELD
ODD FIELD
Figure 5. VSYNC Filter—Odd/Even
DVI RECEIVER
The DVI receiver section of the AD9397 allows the reception of
a digital video stream compatible with DVI 1.0. Embedded in
this data stream are HSYNCs, VSYNCs, and display enable
(DE) signals. DVI restricts the received format to RGB, but the
inclusion of a programmable color space converter (CSC)
allows the output to be tailored to any format necessary. With
this, the scaler following the AD9397 can specify that it always
wishes to receive a particular format—for instance, 4:2:2
YCrCb—regardless of the transmitted mode. If RGB is sent, the
CSC can easily convert that to 4:2:2 YCrCb while relieving the
scaler of this task.
DE GENERATOR
The AD9397 has an onboard generator for DE, for start of
active video (SAV), and for end of active video (EAV), all of
which are necessary for describing the complete data stream for
a BT656-compatible output. In addition to this particular
output, it is possible to generate the DE for cases in which a
scaler is not used. This signal alerts the following circuitry as to
which are displayable video pixels.
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD9397.PDF ] | |
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