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PDF DP83223 Data sheet ( Hoja de datos )
| Número de pieza | DP83223 | |
| Descripción | TWISTER High Speed Networking Transceiver Device | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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April, 1997
DP83223 TWISTER High Speed Networking Transceiver Device
General Description
Features
The DP83223 Twisted Pair Transceiver is an integrated
circuit capable of driving and receiving three-level (MLT-3)
encoded datastreams. The DP83223 Transceiver is
designed to interface directly with National
Semiconductor’s Fast Ethernet and FDDI Chip Sets or
similar Physical Layer silicon allowing low cost data links
over copper based media. The DP83223 allows links of up
to 100 meters over Shielded Twisted Pair (Type-1A STP)
and Category-5 datagrade Unshielded Twisted Pair (Cat-5
UTP) or equivalent. The DP83223 is available in a 28 pin
PLCC package and a 32 pin PQFP package.
s Compatible with ANSI X3.263 TP-PMD draft standard
s Allows use of Type 1 STP and Category 5 UTP cables
s Requires a single +5V supply
s Integrated transmitter and receiver with adaptive equal-
ization circuit
s Isolated TX and RX power supplies for minimum noise
coupling
s Loopback feature for board diagnostics
s Digitally Synthesized transmit signal transition time con-
trol for reduced EMI
s Programmable transmit voltage amplitude
s Suitable for 100BASE-TX Fast Ethernet and Twisted
Pair FDDI applications
System Connection Diagrams
DP83840A
10/100 Ethernet PHY
Scrambled
TX DATA
Scrambled
RX DATA
Signal
Detect
DP83223
Transceiver
PMD
Encoded
TXDATA
PMD
Encoded
RXDATA
Magnetics
SIGDET
DP83257VF or DP83256VF-AP
PLAYER+
TX DATA
Descrambled
Recovered
RXDATA
RX DATA
TXC
Phased
RX CLOCK
Recovered
RXCLOCK
RX DATA
DP83222
Stream Cipher
Scrambled
TX DATA
DP83223
Transceiver
PMD
Encoded
TXDATA
PMD
Encoded
RXDATA
Magnetics
Twisted Pair
Media
100BASE-TX
Twisted Pair
Media
Twisted Pair FDDI
© 1997 National Semiconductor Corporation
1
1 page  
2.0 Pin Description (Continued)
Symbol
Pin No
Type
Description
EQSEL
CDET
PLCC(PQFP)
17(14)
3-Level Se- Equalization Select: This three level Equalization Select input controls the
lect mode of receiver equalization. Forcing a median voltage level,
accomplished by allowing EQSEL to float, selects the adaptive
equalization mode which automatically regulates the equalization effects
based on signal degradation caused by the media. The other two levels are
intended as test modes and are not a guaranteed mode of operation.
Forcing a voltage less than 1.5V, selects full equalization which provides
fixed equalization for a maximum length of cable. Forcing a voltage greater
than 3.0V turns the receive equalizer off.
18(15)
CMOS In
Cable Detect Bar: The active low Cable Detect CMOS input is provided to
support the option of external Cable Detection circuitry (wire fault). With
CDET low, the transceiver functions normally. With CDET high, the signal
detect output is forced low which inhibits data reception by the PHY and
the PMID outputs are forced to ECL static levels. The exception is in the
case of Loopback when the Signal Detect output is forced high regardless
of all other conditions. Please refer to the National Semiconductor Com-
mon Magnetics application note for further detail regarding the proper use
of the DP83223 in a 10/100 Ethernet application.
Revision A
5
5 Page 
4.0 DC and AC Specifications (Continued)
Active PMID
Inactive PMID
SDTHoff
SDTHon
Post Equalized Signal Detect Voltage
Figure 4-2. Post Equalized Signal Detect Voltage
VCC
DP83223
Data from
PHY
Device
0.01uF
SD To PHY
Device
VCC
PMRD+
PMRD-
SD+
SD-
EXTVCC
VCC
TXVCC
TXO+
TXO-
Data to PHY or
Clock Recovery
Device
PMID+
PMID-
float
EQSEL
ENCSEL
CDET
LBEN
GND
RXVCC
RXI+
RXI-
RXGND
TXGND
TXREF
RREF
*510Ω
FB
50Ω
0.01uF
Contact National Semiconductor
for further information relating to
available magnetics modules
50Ω
12.1Ω 12.1Ω
37.9Ω 37.9Ω
Transmit
Magnetics
Receive
Magnetics
1
2
3
4
5
RJ-45
6
7
8
The Receive Attenuation / Termination network
must be optimized to compensate for the insertion
loss of the receive magnetics.
Please refer to the National Semiconductor Application Note
entitled “DP83223 Adaptive Equalization Considerations”
for further detail. The values provided in this example
are targeted to match an insertion loss of approximately
0.4dB (approximately 90mV pk-pk differential of loss for
a typical scrambled IDLE line state) which will result in
a final amplitude of approximately 1.45V pk-pk differential
as seen across the RXI+/- inputs for zero Meters of cable.
0.01uF
Common Mode Noise Filter
GND
The PMRD, SD and PMID 100K ECL differential signal must be
terminated into a standard ECL load of 50Ω to VCC-2.0V or equivalent:
i.e. Thevenin of 130Ω to GND accompanied by 82Ω to VCC
*The Rref resistor value may need to be adjusted
to compensate for transmit magnetics insertion
loss in order to achieve the standard specific
2.0V pk-pk differential TXO+/- output amplitude
as measured across the RJ45 transmit pins.
All resistors are 1/10th Wt, 1% tolerance
All capacitors are 16V ceramic
FB = Murata # BLM31A02PT (1206 package)
Figure 4-3. Typical Schematic for 100BASE-TX signalling over Cat-5 UTP 100Ω cable
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DP83223.PDF ] | |
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