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PDF NCV7382 Data sheet ( Hoja de datos )
| Número de pieza | NCV7382 | |
| Descripción | Enhanced LIN Transceiver | |
| Fabricantes | ON Semiconductor | |
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NCV7382
Advance Information
Enhanced LIN Transceiver
The NCV7382 is a physical layer device for a single wire data link
capable of operating in applications where high data rate is not
required and a lower data rate can achieve cost reductions in both the
physical media components and in the microprocessor which uses
the network. The NCV7382 is designed to work in systems
developed for LIN 1.3 or LIN 2.0. The IC furthermore can be used in
ISO9141 systems.
Because of the very low current consumption of the NCV7382 in
the sleep mode it’s suitable for ECU applications with low standby
current requirements. This mode allows a shutdown of the whole
application. The included wake−up function detects incoming
dominant bus messages and enables the voltage regulator.
Features
• Operating Voltage VS = 6.0 to 18 V
• Very Low Standby Current Consumption of Typ. 6.5 mA in Sleep
Mode
• LIN−Bus Transceiver:
♦ Slew Rate Control for Good EMC Behavior
♦ Fully Integrated Receiver Filter
♦ BUS Input Voltage −27 V to 40 V
♦ Integrated Termination Resistor for LIN Slave Nodes (30 kW)
♦ Wake−Up Via LIN Bus
♦ Baud Rate up to 20 kBaud
♦ Will Work in Systems Designed for Either LIN 1.3 or LIN 2.0
• Compatible to ISO9141 Functions
• High EMI Immunity
• Bus Terminals Protect Against Short−Circuits and Transients in the
Automotive Environment
• High Impedance Bus Pin for Loss of Ground and Undervoltage
Condition
• Thermal Overload Protection
• High Signal Symmetry for use in RC−Based Slave Nodes up to 2%
Clock Tolerance when Compared to the Master Node
• "4.0 kV ESD Protection on BUS, VS and INH Pins
• Control Output for Voltage Regulator with Low On−Resistance for
Switchable Master Termination
• NCV Prefix for Automotive and Other Applications Requiring Site
and Change Control
http://onsemi.com
8
1
SO−8
D SUFFIX
CASE 751
MARKING
DIAGRAM
8
V7382
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
PIN CONNECTIONS
RxD 1
EN 2
VCC 3
TxD 4
8 INH
7 VS
6 BUS
5 GND
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCV7382D
SO−8
95 Units/Rail
NCV7382DR2
SO−8 2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2004
May, 2004 − Rev. P1
1
Publication Order Number:
NCV7382/D
1 page  
NCV7382
ELECTRICAL CHARACTERISTICS (VS = 6.0 to 18 V, VCC = 4.5 to 5.5 V and TA = −40 to 125°C unless otherwise noted.)
Characteristic
Symbol
Condition
Min Typ Max
TXD, EN
High Level Input Voltage
Low Level Input Voltage
TxD Pull Up Resistor
EN Pull Down Resistor
RXD
Low Level Output Voltage
Leakage Current
INH
Vih
Vil
RIH_TXD
RIL_EN
Vol_rxd
Vleak_rxd
Rising Edge
Falling Edge
VTxD = 0 V
VEN = 5.0 V
IRxD = 2.0 mA
VRxD = 5.5 V, Recessive
− − 0.7*VCC
0.3*VCC
−
−
10 15 20
20 30 40
−
−1.0
−
−
0.9
1.0
On Resistance
Leakage Current
Ron_INH
IINH_lk
Normal or Standby Mode,
VINH = VS − 1.0 V, VS = 12 V
EN = L, VINH = 0 V
−
−5.0
20
−
50
5.0
Unit
V
V
kW
kW
V
mA
W
mA
AC CHARACTERISTICS
Characteristic
Symbol
Condition
Min Typ Max Unit
Propagation Delay Transmitter
(Notes 7 and 9)
Propagation Delay Transmitter Symmetry
(Notes 8 and 9)
ttrans_pdf
ttrans_pdr
ttrans_sym
Bus Loads: 1.0 KW/1.0 nF,
660 W/6.8 nF, 500 W/10 nF
Calculate ttrans_pdf − ttrans_pdr
−
−2.0
−
−
5.0 ms
2.0 ms
Propagation Delay Receiver
(Notes 7, 9, 12, 13 and 14)
Propagation Delay Receiver Symmetry
(Notes 9, 11 and 12)
trec_pdf
trec_pdr
trec_sym
CRxD = 20 pF
Calculate ttrans_pdf − ttrans_pdr
−
−1.5
−
−
6.0 ms
1.5 ms
Slew Rate Rising and Falling Edge,
High Battery (Notes 8, 11 and 12)
Slew Rate Rising and Falling Edge,
Low Battery (Notes 8, 11 and 12)
Slope Symmetry, High Battery
(Notes 11 and 12)
Bus Duty Cycle (Note 13)
Receiver Debounce Time
(Notes 8, 11 and 14)
Wake−Up Filter Time
|tSR_HB|
Bus Loads: VS = 18 V,
1.0 2.0 3.0 V/ms
1.0 KW/1.0 nF, 660 W/6.8 nF,
500 W/10 nF
|tSR_LB|
Bus Loads: VS = 7.0 V,
0.5 2.0 3.0 V/ms
1.0 KW/1.0 nF, 660 W/6.8 nF,
500 W/10 nF
tssym_HB
Bus Loads: VS = 18 V,
−5.0
−
+5.0
ms
1.0 KW/1.0 nF, 660 W/6.8 nF,
500 W/10 nF,
Calculate tsdom – tsrec
D1
Calculate tBUS_rec(min)/100 ms
0.396
−
− ms/ms
D2
Calculate tBUS_rec(max)/100 ms
−
− 0.581 ms/ms
trec_deb
BUS Rising and Falling Edge
1.5
−
4.0 ms
twu Sleep Mode,
30 − 150 ms
BUS Rising & Falling Edge
EN − Debounce Time
ten_deb
Normal −> Sleep Mode
Transition
10 20 40 ms
7. Propagation delays are not relevant for LIN protocol transmission, value only information parameter.
8. No production test, guaranteed by design and qualification.
9. See Figure 2 − Input/Output Timing.
10. See Figure 8 − Slope Time Calculation.
11. See Figure 3 − Receiver Debouncing.
12. In accordance to LIN physical layer specification 1.3.
13. In accordance to LIN physical layer specification 2.0.
14. This parameter is tested by applying a square wave to the bus. The minimum slew rate for the bus rising and falling edges is 50 V/ms.
http://onsemi.com
5
5 Page 
NCV7382
System designs can have an external resistor (1 k) in
series with an external diode to the battery, but short circuit
current from bus to ground can be reduced dramatically by
using the INH pin as termination pin for the master pull up
(See Figure 10 − Application Circuitry).
With this new setup, the controller can detect a short
circuit of the bus to ground (RxD timeout) and the
transceiver can be set into sleep mode. The INH pin will be
floating in this case, and the external master pull up resistor
will be disconnected from the bus line. Additionally, the
internal slave termination resistor is switched off and only
a high impedance termination is applied to the bus (typ.
75 mA). This will reduce the failure current of the system
by at least an order of magnitude, preventing a fast
Application Hints
LIN System Parameter
Bus Loading Requirements
Parameter
Operating Voltage Range
Voltage Drop of Reverse Protection Diode
Voltage Drop at the Serial Diode in Pull Up Path
Battery Shift Voltage
Ground Shift Voltage
Master Termination Resistor
Slave Termination Resistor
Number of System Nodes
Total Length of Bus Line
Line Capacitance
Capacitance of Master Node
Capacitance of Slave Node
Total Capacitance of the Bus including Slave and Master
Capacitance
Network Total Resistance
Time Constant of Overall System
discharge of the car battery. If the failure is removed, the
bus level will become recessive again and will wake up the
system even if no local wake−up is present or possible.
Thermal Overload
The NCV7382 is protected against thermal overloads. If
the chip temperature exceeds the thermal shutdown
threshold, the transmitter is switched off until thermal
recovery. The receiver continues to work during thermal
shutdown.
Undervoltage VCC
The VCC undervoltage lockout feature disables the
transmitter until it is above the undervoltage lockout
threshold to prevent undesirable bus traffic.
Symbol
VBAT
VDrop_rev
VSerDiode
VShift_BAT
VShift_GND
Rmaster
Rslave
N
LENBUS
CLINE
CMaster
CSlave
CBUS
RNetwork
τ
Min
8.0
0.4
0.4
0
0
900
20
2.0
−
−
−
−
1.0
537
1.0
Typ
−
0.7
0.7
−
−
1000
30
−
−
100
220
220
4.0
−
−
Max
18
1.0
1.0
0.1
0.1
1100
60
16
40
150
−
250
10
863
5.0
Unit
V
V
V
VBAT
VBAT
W
kW
−
m
pF/m
pF
pF
nF
W
ms
Recommendations for System Design
The goal of the LIN physical layer standard is to have a
universal definition of the LIN system for plug and play
solutions in LIN networks up to 20 kbd bus speeds.
In case of small and medium LIN networks, it’s
recommended to adjust the total network capacitance to at
least 4.0 nF for good EMC and EMI behavior. This can be
done by setting only the master node capacitance. The
slave node capacitance should have a unit load of typically
220 pF for good EMC/EMI behavior.
In large networks with long bus lines and the maximum
number of nodes, some system parameters can exceed the
defined limits and of the LIN system designer must
intervene.
The whole capacitance of a slave node is not only the unit
load capacitor itself. Additionally, there is the capacitance
of wires and connectors, and the internal capacitance of the
LIN transmitter. This internal capacitance is strongly
dependent on the technology of the IC manufacturer and
should be in the range of 30 pF to 150 pF. If the bus lines
have a total length of nearly 40m, the total bus capacitance
can exceed the LIN system limit of 10 nF.
A second parameter of concern is the integrated slave
termination resistor tolerance. If most of the slave nodes
have a slave termination resistance at the allowed
maximum of 60 kW, the total network resistance is more
than 700 W. Even if the total network capacitance is below
or equal to the maximum specified value of 10 nF, the
network time constant is higher than 7.0 ms.
This problem can be solved only by adjusting the master
termination resistor to the required maximum network time
constant of 5.0 ms (max).
http://onsemi.com
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet NCV7382.PDF ] | |
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