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PDF AD7747 Data sheet ( Hoja de datos )
| Número de pieza | AD7747 | |
| Descripción | 24-Bit Capacitance-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7747 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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24-Bit Capacitance-to-Digital Converter
with Temperature Sensor
AD7747
FEATURES
GENERAL DESCRIPTION
Capacitance-to-digital converter
New standard in single chip solutions
Interfaces to single or differential grounded sensors
Resolution down to 20 aF (that is, up to 19.5-bit ENOB)
Accuracy: 10 fF
Linearity: 0.01%
Common-mode (not changing) capacitance up to 17 pF
Full-scale (changing) capacitance range ±8 pF
Update rate: 5 Hz to 45 Hz
Simultaneous 50 Hz and 60 Hz rejection at 8.1 Hz update
Active shield for shielding sensor connection
Temperature sensor on-chip
Resolution: 0.1°C, accuracy: ±2°C
Voltage input channel
Internal clock oscillator
2-wire serial interface (I2C® compatible)
Power
2.7 V to 5.25 V single-supply operation
0.7 mA current consumption
Operating temperature: −40°C to +125°C
16-lead TSSOP package
APPLICATIONS
Automotive, industrial, and medical systems for
Pressure measurement
Position sensing
Proximity sensing
Level sensing
Flow metering
Impurity detection
The AD7747 is a high-resolution, Σ-Δ capacitance-to-digital
converter (CDC). The capacitance to be measured is connected
directly to the device inputs. The architecture features inherent
high resolution (24-bit no missing codes, up to 19.5-bit effective
resolution), high linearity (±0.01%), and high accuracy (±10 fF
factory calibrated). The AD7747 capacitance input range is
±8 pF (changing), and it can accept up to 17 pF common-mode
capacitance (not changing), which can be balanced by a program-
mable on-chip digital-to-capacitance converter (CAPDAC).
The AD7747 is designed for single-ended or differential
capacitive sensors with one plate connected to ground. For
floating (not grounded) capacitive sensors, the AD7745 or
AD7746 are recommended.
The part has an on-chip temperature sensor with a resolution of
0.1°C and accuracy of ±2°C. The on-chip voltage reference and
the on-chip clock generator eliminate the need for any external
components in capacitive sensor applications. The part has a
standard voltage input that, together with the differential reference
input, allows easy interface to an external temperature sensor,
such as an RTD, thermistor, or diode.
The AD7747 has a 2-wire, I2C-compatible serial interface. The
part can operate with a single power supply of 2.7 V to 5.25 V.
It is specified over the automotive temperature range of
−40°C to +125°C and is housed in a 16-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN(+)
TEMP
SENSOR
CLOCK
GENERATOR
AD7747
VIN(–)
CIN1(+)
CIN1(–)
SHLD
MUX
24-BIT Σ-Δ
GENERATOR
DIGITAL
FILTER
I2C
SERIAL
INTERFACE
EXCITATION
CAP DAC 1
CAP DAC 2
CONTROL LOGIC
CALIBRATION
VOLTAGE
REFERENCE
SDA
SCL
RDY
REFIN(+) REFIN(–)
Figure 1.
GND
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
AD7747
Parameter
Normal Mode Rejection5
Min
Common-Mode Rejection2
INTERNAL VOLTAGE REFERENCE
Voltage
Drift vs. Temperature
EXTERNAL VOLTAGE REFERENCE INPUT
Differential REFIN Voltage2
Absolute REFIN Voltage2
Average REFIN Input Current
Average REFIN Input Current Drift
Common-Mode Rejection
SERIAL INTERFACE LOGIC INPUTS (SCL, SDA)
VIH Input High Voltage
VIL Input Low Voltage
Hysteresis
Input Leakage Current (SCL)
OPEN-DRAIN OUTPUT (SDA)
VOL Output Low Voltage
IOH Output High Leakage Current
LOGIC OUTPUT (RDY)
VOL Output Low Voltage
VOH Output High Voltage
VOL Output Low Voltage
VOH Output High Voltage
POWER REQUIREMENTS
VDD-to-GND Voltage
IDD Current
1.169
0.1
GND − 0.03
2.1
4.0
VDD − 0.6
4.75
2.7
IDD Current Power-Down Mode
Typ
75
50
95
1.17
5
2.5
400
±50
80
150
±0.1
0.1
750
700
0.5
Max Unit
dB
dB
dB
1.171
V
ppm/°C
VDD
VDD + 0.03
V
V
nA/V
pA/V/°C
dB
V
0.8 V
mV
±1 μA
0.4 V
1 μA
0.4 V
V
0.4 V
V
5.25 V
3.6 V
850 μA
μA
μA
2 μA
Test Conditions/Comments
50 Hz ± 1%, conversion time = 122.1 ms
60 Hz ± 1%, conversion time = 122.1 ms
VIN = 1 V
TA = 25°C
ISINK = −6.0 mA
VOUT = VDD
ISINK = 1.6 mA, VDD = 5 V
ISOURCE = 200 μA, VDD = 5 V
ISINK = 100 μA, VDD = 3 V
ISOURCE = 100 μA, VDD = 3 V
VDD = 5 V, nominal
VDD = 3.3 V, nominal
Digital inputs equal to VDD or GND
VDD = 5 V
VDD = 3.3 V
Digital inputs equal to VDD or GND
1 Capacitance units: 1 pF = 10−12 F; 1 fF = 10−15 F; 1 aF = 10−18 F. Full scale (FS) = 8.192 pF; full-scale range (FSR) = ±8.192 pF.
2 Specification is not production tested, but is supported by characterization data at initial product release.
3 Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C.
At different temperatures, compensation for gain drift over temperature is required.
4 The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register
LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter +
system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF; the larger
offset can be removed using CAPDACs.
5 Specification is not production tested, but guaranteed by design.
6 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.
7 The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance.
8 Using an external temperature sensing diode 2N3906, with nonideality factor nf = 1.008, connected as in Figure 37, with total serial resistance <100 Ω.
9 Full-scale error applies to both positive and negative full scale.
Rev. 0 | Page 4 of 28
5 Page 
AD7747
200
150
100
50
0
–50
–100
–150
–200
0
8 16 24 32 40 48 56 64
CAPDAC CODE
Figure 16. CAPDAC Differential Nonlinearity (DNL)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–50
–25
0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 17. Internal Temperature Sensor Error vs. Temperature
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–50
–25
0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 18. External Temperature Sensor Error vs. Temperature
0
–20
–40
–60
–80
–100
–120
0
100 200 300 400 500 600 700 800 900
INPUT SIGNAL FREQUENCY (Hz)
1k
Figure 19. Capacitive Channel Frequency Response;
Conversion Time = 22 ms
0
–20
–40
–60
–80
–100
–120
0
25 50 75 100 125 150 175 200
INPUT SIGNAL FREQUENCY (Hz)
Figure 20. Capacitive Channel Frequency Response;
Conversion Time = 124 ms
0
–20
–40
–60
–80
–100
–120
0
50 100 150 200 250 300 350 400
INPUT SIGNAL FREQUENCY (Hz)
Figure 21. Voltage Channel Frequency Response;
Conversion Time = 122.1 ms
Rev. 0 | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD7747.PDF ] | |
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