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PDF ADSP-TS101S Data sheet ( Hoja de datos )
| Número de pieza | ADSP-TS101S | |
| Descripción | Embedded Processor | |
| Fabricantes | Analog Devices | |
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a
T
Embedded Processor
ADSP-TS101S
KEY FEATURES
300 MHz, 3.3 ns Instruction Cycle Rate
6M Bits of Internal—On-Chip—SRAM Memory
19 mm ؋ 19 mm (484-Ball) or 27 mm ؋ 27 mm
(625-Ball) PBGA Package
Dual Computation Blocks—Each Containing an ALU, a
Multiplier, a Shifter, and a Register File
Dual Integer ALUs, Providing Data Addressing and
Pointer Manipulation
Integrated I/O Includes 14 Channel DMA Controller,
External Port, Four Link Ports, SDRAM Controller,
Programmable Flag Pins, Two Timers, and Timer
Expired Pin for System Integration
1149.1 IEEE Compliant JTAG Test Access Port for
On-Chip Emulation
On-Chip Arbitration for Glueless Multiprocessing with
up to Eight TigerSHARC Processors on a Bus
KEY BENEFITS
Provides High Performance Static Superscalar DSP
Operations, Optimized for Telecommunications
Infrastructure and Other Large, Demanding
Multiprocessor DSP Applications
Performs Exceptionally Well on DSP Algorithm and I/O
Benchmarks (See Benchmarks in Table 1 and Table 2)
Supports Low Overhead DMA Transfers Between
Internal Memory, External Memory, Memory-Mapped
Peripherals, Link Ports, Host Processors, and Other
(Multiprocessor) DSPs
Eases DSP Programming Through Extremely Flexible
Instruction Set and High Level Language Friendly DSP
Architecture
Enables Scalable Multiprocessing Systems with Low
Communications Overhead
FUNCTIONAL BLOCK DIAGRAM
COMPUTATIONAL BLOCKS
SHIFTER
ALU
MULTIPLIER
X
REGISTER
FILE
32x32
128 128
DAB
DAB
128 128
Y
REGISTER
FILE
32x32
MULTIPLIER
ALU
SHIFTER
PROGRAM SEQUENCER
PC BTB IRQ
ADDR
IAB FETCH
DATA ADDRESS GENERATION
INTEGER 32
J ALU
32 INTEGER
K ALU
32x32
32x32
32
128
32
128
32
128
I/O PROCESSOR
DMA
CONTROLLER
CONTROL/
STATUS/
TCBs
DMA ADDRESS
DMA DATA
INTERNAL MEMORY
MEMORY MEMORY MEMORY
M0 M1 M2
64Kx32 64Kx32 64Kx32
A DA DA D
6
JTAG PORT
SDRAM CONTROLLER
32 256
M0 ADDR
M0 DATA
M1 ADDR
M1 DATA
EXTERNAL PORT
MULTIPROCESSOR
INTERFACE
HOST INTERFACE
INPUT FIFO
32
ADDR
64
OUTPUT BUFFER
DATA
M2 ADDR
M2 DATA
I/O ADDRESS 32
OUTPUT FIFO
CLUSTER BUS
ARBITER
CNTRL
3
LINK PORT
CONTROLLER
L0 8
3
256 LINK DATA
L1
LINK
PORTS
8
3
CONTROL/
STATUS/
BUFFERS
L2 8
3
L3 8
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
1 page  
ADSP-TS101S
• Branch prediction encoded in instruction, enables zero-
overhead loops
• Parallelism encoded in instruction line
• Conditional execution optional for all instructions
• User-defined, programmable partitioning between
program and data memory
On-Chip SRAM Memory
The ADSP-TS101S has 6M bits of on-chip SRAM memory,
divided into three blocks of 2M bits (64K words × 32 bits). Each
block—M0, M1, and M2—can store program, data, or both, so
applications can configure memory to suit specific needs. Placing
program instructions and data in different memory blocks,
however, enables the DSP to access data while performing an
instruction fetch.
The DSP’s internal and external memory (Figure 2) is organized
into a unified memory map, which defines the location (address)
of all elements in the system.
The memory map is divided into four memory areas—host space,
external memory, multiprocessor space, and internal memory—
and each memory space, except host memory, is subdivided into
smaller memory spaces.
Each internal memory block connects to one of the 128-bit wide
internal buses—block M0 to bus MD0, block M1 to bus MD1,
and block M2 to bus MD2—enabling the DSP to perform three
memory transfers in the same cycle. The DSP’s internal bus
architecture provides a total memory bandwidth of 14.4G bytes
per second, enabling the core and I/O to access eight 32-bit data
words (256 bits) and four 32-bit instructions each cycle. The
DSP’s flexible memory structure enables:
• DSP core and I/O access of different memory blocks in
the same cycle
• DSP core access of all three memory blocks in parallel—
one instruction and two data accesses
• Programmable partitioning of program and data memory
• Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
• Complete context switch in less than 20 cycles (66 ns)
External Port (Off-Chip Memory/Peripherals Interface)
The ADSP-TS101S processor’s external port provides the pro-
cessor’s interface to off-chip memory and peripherals. The
4G word address space is included in the DSP’s unified address
space. The separate on-chip buses—three 128-bit data buses and
three 32-bit address buses—are multiplexed at the external port
to create an external system bus with a single 64-bit data bus and
a single 32-bit address bus. The external port supports data
transfer rates of 800M bytes per second over external bus.
The external bus can be configured for 32- or 64-bit operation.
When the system bus is configured for 64-bit operation, the lower
32 bits of the external data bus connect to even addresses, and
the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory
mapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
The ADSP-TS101S provides programmable memory, pipeline
depth, and idle cycle for synchronous accesses, and external
acknowledge controls to support interfacing to pipelined or slow
devices, host processors, and other memory-mapped peripherals
with variable access, hold, and disable time requirements.
Host Interface
The ADSP-TS101S provides an easy and configurable interface
between its external bus and host processors through the external
port. To accommodate a variety of host processors, the host
interface supports pipelined or slow protocols for accesses of the
host as slave. Each protocol has programmable transmission
parameters, such as idle cycles, pipe depth, and internal
wait cycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST signal, the DSP increments the address
internally while the host continues to assert BRST.
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF signal provides the deadlock recovery mecha-
nism. When the host asserts BOFF, the DSP backs off the current
transaction and asserts HBG and relinquishes the external bus.
The host can directly read or write the internal memory of the
ADSP-TS101S, and it can access most of the DSP registers,
including DMA control (TCB) registers. Vector interrupts
support efficient execution of host commands.
Multiprocessor Interface
The ADSP-TS101S offers powerful features tailored to multi-
processing DSP systems through the external port and link ports.
This multiprocessing capability provides highest bandwidth for
interprocessor communication, including:
• Up to eight DSPs on a common bus
• On-chip arbitration for glueless multiprocessing
• Link ports for point-to-point communication
The external port and link ports provide integrated, glueless mul-
tiprocessing support.
The external port supports a unified address space (see Figure 2)
that enables direct interprocessor accesses of each ADSP-
TS101S processor’s internal memory and registers. The DSP’s
on-chip distributed bus arbitration logic provides simple, glueless
connection for systems containing up to eight ADSP-TS101S
processors and a host processor. Bus arbitration has a rotating
priority. Bus lock supports indivisible read-modify-write
sequences for semaphores. A bus fairness feature prevents one
DSP from holding the external bus too long.
The DSP’s four link ports provide a second path for interproces-
sor communications with throughput of 1G bytes per second.
The cluster bus provides 800M bytes per second throughput—
with a total of 1.8G bytes per second interprocessor bandwidth.
REV. A
–5–
5 Page 
ADSP-TS101S
the Analog Devices website (www.analog.com)—use site search
on “EE-68.” This document is updated regularly to keep pace
with improvements to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-TS101S
processor’s architecture and functionality. For detailed informa-
tion on the ADSP-TS101S processor’s core architecture and
instruction set, see the ADSP-TS101 TigerSHARC Processor Pro-
gramming Reference and the ADSP-TS101 TigerSHARC Processor
Hardware Reference. For detailed information on the development
tools for this processor, see the VisualDSP++ User’s Guide for
TigerSHARC Processors.
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS101S processor’s input pins are
normally synchronous—tied to a specific clock—a few are asyn-
chronous. For these asynchronous signals, an on-chip
synchronization circuit prevents metastability problems. The
synchronous ac specification for asynchronous signals is used
only when predictable cycle-by-cycle behavior is required.
All inputs are sampled by a clock reference, therefore input spec-
ifications (asynchronous minimum pulsewidths or synchronous
input setup and hold) must be met to guarantee recognition.
Pin States at Reset
The output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these pins
to get to their internal pull-up or pull-down state. Some output
pins (control signals) have a pull-up or pull-down that maintains
a known value during transitions between different drivers.
Pin Definitions
The Type column in the following pin definitions tables describes
the pin type, when the pin is used in the system. The Term (for
termination) column describes the pin termination type if the pin
is not used by the system. Note that some pins are always used
(indicated with au symbol).
Table 3. Pin Definitions—Clocks and Reset
Signal
Type
Term Description
LCLK_N
LCLK_P
I
I
LCLKRAT2–01
I (pd2)
SCLK_N
SCLK_P
I
I
SCLKFREQ3
RESET
I (pu2)
I/A
au Local Clock Reference. Connect this pin to VREF as shown in Figure 5.
au Local Clock Input. DSP clock input. The instruction cycle rate = n × LCLK,
where n is user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6. See Clock Domains
on Page 9.
au LCLK Ratio. The DSP’s core clock (instruction cycle rate) = n × LCLK, where
n is user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6 as shown in Table 4. These
pins must have a constant value while the DSP is powered.
au System Clock Reference. Connect this pin to VREF as shown in Figure 5.
au System Clock Input. The DSP’s system input clock for cluster bus. This pin
must be connected to the same clock source as LCLK_P. See Clock Domains
on Page 9.
au SCLK Frequency. SCLKFREQ = 1 is required. The SCLKFREQ pin must
have a constant value while the DSP is powered.
au Reset. Sets the DSP to a known state and causes program to be in idle state.
RESET must be asserted at specified time according to the type of reset
operation. For details, see Reset and Booting on Page 8.
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 kΩ to VSS; epu = External pull-up approximately 10 kΩ to VDD-IO
nc = Not connected; au = Always used.
1 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
2 See ELECTRICAL CHARACTERISTICS on Page 19 for maximum and minimum current consumption for pull-up and pull-down resistances.
3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Table 4. LCLK Ratio
LCLKRAT2–0
000 (default)
001
010
011
100
Ratio
2
2.5
3
3.5
4
Table 4. LCLK Ratio (continued)
LCLKRAT2–0
101
110
111
Ratio
5
6
Reserved
REV. A
–11–
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