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PDF AD9957 Data sheet ( Hoja de datos )
| Número de pieza | AD9957 | |
| Descripción | 1 GSPS Quadrature Digital Upconverter | |
| Fabricantes | Analog Devices | |
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Data Sheet
1 GSPS Quadrature Digital Upconverter
with 18-Bit I/Q Data Path and 14-Bit DAC
AD9957
FEATURES
1 GSPS internal clock speed (up to 400 MHz analog output)
Integrated 1 GSPS 14-bit DAC
250 MSPS input data rate
Phase noise ≤ −125 dBc/Hz (400 MHz carrier @ 1 kHz offset)
Excellent dynamic performance >80 dB narrow-band SFDR
8 programmable profiles for shift keying
Sin(x)/(x) correction (inverse sinc filter)
Reference clock multiplier
Internal oscillator for a single crystal operation
Software and hardware controlled power-down
Integrated RAM
Phase modulation capability
Multichip synchronization
Easy interface to Blackfin SPORT
Interpolation factors from 4× to 252×
Interpolation DAC mode
Gain control DAC
Internal divider allows references up to 2 GHz
1.8 V and 3.3 V power supplies
100-lead TQFP_EP package
APPLICATIONS
HFC data, telephony, and video modems
Wireless base station transmissions
Broadband communications transmissions
Internet telephony
GENERAL DESCRIPTION
The AD9957 functions as a universal I/Q modulator and agile
upconverter for communications systems where cost, size, power
consumption, and dynamic performance are critical. The
AD9957 integrates a high speed, direct digital synthesizer
(DDS), a high performance, high speed, 14-bit digital-to-analog
converter (DAC), clock multiplier circuitry, digital filters, and
other DSP functions onto a single chip. It provides baseband
upconversion for data transmission in a wired or wireless
communications system.
The AD9957 is the third offering in a family of quadrature
digital upconverters (QDUCs) that includes the AD9857 and
AD9856. It offers performance gains in operating speed, power
consumption, and spectral performance. Unlike its predecessors,
it supports a 16-bit serial input mode for I/Q baseband data.
The device can alternatively be programmed to operate either as
a single tone, sinusoidal source or as an interpolating DAC.
The reference clock input circuitry includes a crystal oscillator,
a high speed, divide-by-two input, and a low noise PLL for
multiplication of the reference clock frequency.
The user interface to the control functions includes a serial port
easily configured to interface to the SPORT of the Blackfin®
DSP and profile pins to enable fast and easy shift keying of any
signal parameter (phase, frequency, or amplitude).
I/Q DATA
FUNCTIONAL BLOCK DIAGRAM
FORMAT AND
INTERPOLATE
I
Q
14-BIT DAC
NCO AD9957
DATA
FOR
XMIT
TIMING
AND
CONTROL
REFERENCE CLOCK
INPUT CIRCUITRY
USER INTERFACE
REFERENCE CLOCK INPUT
Figure 1.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9957
REVISION HISTORY
1/16—Rev. C to Rev. D
Changes to Table 3.......................................................................... 11
Changes to Figure 27...................................................................... 18
4/12—Rev. B to Rev. C
Changes to Table 1............................................................................ 7
Changes to Table 3.......................................................................... 11
Change to Sync Generator Section............................................... 41
Changes to Sync Receiver Section and Setup/Hold Validation
Section.............................................................................................. 42
Changes to Table 13........................................................................ 50
Changes to Table 19........................................................................ 57
Changes to Table 26........................................................................ 59
10/10—Rev. A to Rev. B
Changes to Data Rate in Features Section..................................... 1
Changes to Specifications Section.................................................. 6
Added EPAD Notation to Figure 4 and Table 3............................ 9
Changes to XTAL_SEL Pin Description...................................... 11
Changes to BlackFin Interface (BFI) Mode Section .................. 18
Changes to Figure 30 and Figure 31............................................. 22
Changes to Programmable Interpolating Filter Section............ 24
Changes to Fifth Paragraph of Quadrature Modulator Section .....25
Changes to RAM Segment Registers Section ............................. 27
Changes to RAM Playback Operation Section........................... 28
Changes to Control Interface—Serial I/O Section..................... 47
Added to I/O_UPDATE, SYNC_CLK, and System Clock
Relationships Section and Figure 64 ............................................ 49
Changes to Default Values of Profile 0 Register—Single Tone
(0x0E) and Profile 0 Register—QDUC (0x0E) in Table 14....... 51
Changes to Default Values in Table 15......................................... 52
Changes to Default Values in Table 16......................................... 53
Changes to Default Values in Table 17......................................... 54
Updated Outline Dimensions ....................................................... 61
Data Sheet
1/08—Rev. 0 to Rev. A
Changes to REFCLK Multiplier Specification...............................3
Changes to I/O_Update/Profile<2:0>/RT Timing
Characteristics and I/Q Input Timing Characteristics.................5
Replaced Pin Configuration and Function Descriptions
Section.................................................................................................8
Changes to Figure 25 Through Figure 29.................................... 15
Deleted Table 4, Renumbered Sequentially ................................ 20
Changes to DDS Core Section...................................................... 24
Changes to Figure 47 and Table 6................................................. 33
Replaced Synchronization of Multiple Devices Section............ 39
Added I/Q Path Latency Section.................................................. 44
Added Power Supply Partitioning Section.................................. 45
Changes to General Serial I/O Operation Section..................... 46
Changes to Table 13 ....................................................................... 48
Changes to Table 14 ....................................................................... 49
Changes to Table 19 ....................................................................... 54
Changes to Table 20 ....................................................................... 56
Changes to GPIO Configuration Register and
GPIO Data Register Sections ........................................................ 58
5/07—Revision 0: Initial Version
Rev. D | Page 4 of 64
5 Page 
AD9957
Data Sheet
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
I/O1 Description
1, 24, 61, 72, 86,
87, 93, 97 to 100
2
3, 6, 89, 92
74 to 77, 83
17, 23, 30, 47, 57,
64
11, 15, 21, 28, 45,
56, 66
4, 5, 73, 78, 79,
82, 85, 88, 96
13, 16, 22, 29, 46,
58, 62, 63, 65
7
NC
PLL_LOOP_FILTER
AVDD (1.8V)
AVDD (3.3V)
DVDD (1.8V)
DVDD_I/O (3.3V)
AGND
DGND
SYNC_IN+
I
I
I
I
I
I
I
I
8
SYNC_IN−
I
9
SYNC_OUT+
O
10
SYNC_OUT−
O
12 SYNC_SMP_ERR O
14 MASTER_RESET I
18 EXT_PWR_DWN I
19
20
25 to 27, 31 to
39, 42 to 44, 48
to 50
42
43
40
41
PLL_LOCK
CCI_OVFL
D<17:0>
SPORT I-DATA
SPORT Q-DATA
PDCLK
TxENABLE/FS
O
O
I/O
I
I
O
I
Not Connected. Allow the device pin to float.
PLL Loop Filter Compensation. See External PLL Loop Filter Components section.
Analog Core VDD. 1.8 V analog supplies.
Analog DAC VDD. 3.3 V analog supplies.
Digital Core VDD. 1.8 V digital supplies.
Digital Input/Output VDD. 3.3 V digital supplies.
Analog Ground.
Digital Ground.
Synchronization Signal, Digital Input (Rising Edge Active). Synchronization signal from
external master to synchronize internal subclocks. See the Synchronization of Multiple
Devices section.
Synchronization Signal, Digital Input (Falling Edge Active). Synchronization signal from
external master to synchronize internal subclocks. See the Synchronization of Multiple
Devices section.
Synchronization Signal, Digital Output (Rising Edge Active). Synchronization signal from
internal device subclocks to synchronize external slave devices. See the Synchronization of
Multiple Devices section.
Synchronization Signal, Digital Output (Falling Edge Active). Synchronization signal from
internal device subclocks to synchronize external slave devices. See the Synchronization of
Multiple Devices section.
Synchronization Sample Error, Digital Output (Active High). A high on this pin indicates
that the AD9957 did not receive a valid sync signal on SYNC_IN+/SYNC_IN−. See the
Synchronization of Multiple Devices section.
Master Reset, Digital Input (Active High). This pin clears all memory elements and sets
registers to default values.
External Power-Down, Digital Input (Active High). A high level on this pin initiates the
currently programmed power-down mode. See the Power-Down Control section for
further details. If unused, tie to ground.
PLL Lock, Digital Output (Active High). A high on this pin indicates that the clock multiplier
PLL has acquired lock to the reference clock input.
CCI Overflow Digital Output, Active High. A high on this pin indicates a CCI filter overflow.
This pin remains high until the CCI overflow condition is cleared.
Parallel Data Input Bus (Active High). These pins provide the interleaved, 18-bit, digital, I
and Q vectors for the modulator to upconvert. Also used for a GPIO port in Blackfin
interface mode.
I-Data Serial Input. In Blackfin interface mode, this pin serves as the I-data serial input.
Q-Data Serial Input. In Blackfin interface mode, this pin serves as the Q-data serial input.
Parallel Data Clock, Digital Output (Clock). See the Signal Processing section for details.
Transmit Enable, Digital Input (Active High). See the Signal Processing section for details.
In Blackfin interface mode, this pin serves as the FS input to receive the RFS output signal
from the Blackfin.
51
52 to 54
55
RT
PROFILE<2:0>
SYNC_CLK
I RAM Trigger, Digital Input (Active High). This pin provides control for the RAM amplitude
scaling function. When this function is engaged, a high sweeps the amplitude from the
beginning RAM address to the end. A low sweeps the amplitude from the end RAM
address to the beginning. If unused, connect to ground or supply.
I Profile Select Pins, Digital Inputs (Active High). These pins select one of eight
phase/frequency profiles for the DDS core (single tone or carrier tone). Changing the state
of one of these pins transfers the current contents of all I/O buffers to the corresponding
registers. Set up state changes to the SYNC_CLK pin.
O Output System Clock/4, Digital Output (Clock). Set up the I/O_UPDATE and PROFILE<2:0>
pins to the rising edge of this signal.
Rev. D | Page 10 of 64
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9957.PDF ] | |
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