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PDF AD9734 Data sheet ( Hoja de datos )
| Número de pieza | AD9734 | |
| Descripción | 1200 MSPS DACS | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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10-/12-/14-Bit, 1200 MSPS DACS
AD9734/AD9735/AD9736
FEATURES
Pin-compatible family
Excellent dynamic performance
AD9736: SFDR = 82 dBc at fOUT = 30 MHz
AD9736: SFDR = 69 dBc at fOUT = 130 MHz
AD9736: IMD = 87 dBc at fOUT = 30 MHz
AD9736: IMD = 82 dBc at fOUT = 130 MHz
LVDS data interface with on-chip 100 Ω terminations
Built-in self test
LVDS sampling integrity
LVDS-to-DAC data transfer integrity
Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz)
1.8/3.3 V dual-supply operation
Adjustable analog output
8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω)
On-chip 1.2 V reference
160-lead chip scale ball grid array (CSP_BGA) package
APPLICATIONS
Broadband communications systems
Cellular infrastructure (digital predistortion)
Point-to-point wireless
CMTS/VOD
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The AD9736, AD9735, and AD9734 are high performance, high
frequency DACs that provide sample rates of up to 1200 MSPS,
permitting multicarrier generation up to their Nyquist
frequency. The AD9736 is the 14-bit member of the family,
while the AD9735 and the AD9734 are the 12-bit and 10-bit
members, respectively. They include a serial peripheral interface
(SPI) port that provides for programming of many internal
parameters and enables readback of status registers.
A reduced-specification LVDS interface is utilized to achieve
the high sample rate. The output current can be programmed
over a range of 8.66 mA to 31.66 mA. The AD973x family is
manufactured on a 0.18 μm CMOS process and operates from
1.8 V and 3.3 V supplies for a total power consumption of
380 mW in bypass mode. It is supplied in a 160-lead chip scale
ball grid array for reduced package parasitics.
FUNCTIONAL BLOCK DIAGRAM
RESET
S1 S2 S3
IRQ
DACCLK– DACCLK+
SDIO
SDO
CSB
SCLK
C1
SPI CONTROLLER C2
C3 C3
DATACLK_OUT+
DATACLK_OUT–
CLOCK
DISTRIBUTION
S3
DATACLK_IN+
DATACLK_IN–
DB[13:0]+
DB[13:0]–
2×
14-, 12-,
IOUTA
10-BIT DAC
CORE
IOUTB
C2 BAND GAP
C1S1
REFERENCE
CURRENT S2
VREF
I120
Figure 1.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) features
enable high quality synthesis of wideband signals at inter-
mediate frequencies up to 600 MHz.
2. Double data rate (DDR) LVDS data receivers support the
maximum conversion rate of 1200 MSPS.
3. Direct pin programmability of basic functions or SPI port
access offers complete control of all AD973x family
functions.
4. Manufactured on a CMOS process, the AD973x family
uses a proprietary switching technique that enhances
dynamic performance.
5. The current output(s) of the AD9736 family are easily con-
figured for single-ended or differential circuit topologies.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD9734/AD9735/AD9736
Parameter
Static, No Clock
IAVDD33
ICVDD18
IDVDD33
IDVDD18
FIR Bypass (1×) Mode
Sleep Mode, No Clock
IAVDD33
FIR Bypass (1×) Mode
Power-Down Mode3
IAVDD33
ICVDD18
IDVDD33
IDVDD18
FIR Bypass (1×) Mode
AD9736
AD9735
AD9734
Min Typ
Max Min Typ
Max Min Typ
Max Unit
25 25 25 mA
8 8 8 mA
10 10 10 mA
2 2 2 mA
133 133 133 mW
2.5 3.15
59 65
2.5 3.15
59 65
2.5 3.15 mA
59 65 mW
0.01 0.13
0.02 0.12
0.01 0.12
0.01 0.11
0.12 1.24
0.01 0.13
0.02 0.12
0.01 0.12
0.01 0.11
0.12 1.24
0.01 0.13 mA
0.02 0.12 mA
0.01 0.12 mA
0.01 0.11 mA
0.12 1.24 mW
1 Default band gap adjustment (Reg. 0x0E <2:0> = 0x0).
2 Use an external amplifier to drive any external load.
3 Typical wake-up time is 8 μs with recommended 1 nF capacitor on VREF pin.
Rev. A | Page 5 of 72
5 Page 
AD9734/AD9735/AD9736
Pin No.
K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6,
L9, L10, L11, L12, M3, M4, M5, M6, M9,
M10, M11, M12
K13, K14
Mnemonic
DVSS
DB<13>−/DB<13>+
L1 PIN_MODE
L7, L8, M7, M8, N7, N8, P7, P8
L13, L14
M2, M1
M13, M14
N1, P1
N2, P2
N3, P3
N4, P4
N5, P5
N6, P6
N9, P9
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
DVDD33
DB<12>−/DB<12>+
DB<0>−/DB<0>+
DB<11>−/DB<11>+
DB<1>−/DB<1>+
DB<2>−/DB<2>+
DB<3>−/DB<3>+
DB<4>−/DB<4>+
DB<5>−/DB<5>+
DATACLK_OUT−/
DATACLK_OUT+
DATACLK_IN−/
DATACLK_IN+
DB<6>−/DB<6>+
DB<7>−/DB<7>+
DB<8>−/DB<8>+
DB<9>−/DB<9>+
DB<10>−/DB<10>+
Description
Digital Supply Ground.
Negative/Positive Data Input Bit 13 (MSB). Conforms to IEEE-1596
reduced range link.
0 = SPI Mode. SPI is enabled.
1 = PIN Mode. SPI is disabled; direct pin control.
3.3 V Digital Supply.
Negative/Positive Data Input Bit 12. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596
reduced range link.
Negative/Positive Data Input Bit 11. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Output Clock. Conforms to IEEE-1596
reduced range link.
Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 9. Conforms to IEEE-1596 reduced
range link.
Negative/Positive Data Input Bit 10. Conforms to IEEE-1596 reduced
range link.
Rev. A | Page 11 of 72
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9734.PDF ] | |
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