IDT72T3685 Datasheet PDF - Integrated Device Technology
| Part Number | IDT72T3685 | |
| Description | (IDT72T36xxx) 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS | |
| Manufacturers | Integrated Device Technology | |
| Logo |  |
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2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
1,024 x 36, 2,048 x 36, 4,096 x 36,
8,192 x 36, 16,384 x 36, 32,768 x 36,
65,536 x 36, 131,072 x 36 and 262,144 x 36
IDT72T3645, IDT72T3655, IDT72T3665,
IDT72T3675, IDT72T3685, IDT72T3695,
IDT72T36105, IDT72T36115, IDT72T36125
FEATURES:
• Choose among the following memory organizations:
IDT72T3645 1,024 x 36
IDT72T3655 2,048 x 36
IDT72T3665 4,096 x 36
IDT72T3675 8,192 x 36
IDT72T3685 16,384 x 36
IDT72T3695 32,768 x 36
IDT72T36105 65,536 x 36
IDT72T36115 131,072 x 36
IDT72T36125 262,144 x 36
• Up to 225 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Read Enable & Read Clock Echo outputs aid high speed operation
• User selectable Asynchronous read and/or write port timing
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input enables/disables Write operations
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Separate SCLK input for Serial programming of flag offsets
• User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 208-pin (17mm x 17mm) or 240-pin (19mm x 19mm)
Plastic Ball Grid Array (PBGA)
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK/WR
D0 -Dn (x36, x18 or x9)
LD SEN SCLK
WCS
INPUT REGISTER
OFFSET REGISTER
ASYW
BE
IP
WRITE CONTROL
LOGIC
WRITE POINTER
CONTROL
LOGIC
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
262,144 x 36
FLAG
LOGIC
READ POINTER
BM
IW
OW
MRS
PRS
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
TCK
TRST
TMS
TDO
TDI
Vref
WHSTL
RHSTL
SHSTL
JTAG CONTROL
(BOUNDARY SCAN)
HSTL I/0
CONTROL
OE
Q0 -Qn (x36, x18 or x9)
EREN
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
RT
MARK
ASYR
RCLK/RD
REN
RCS
5907 drw01
SEPTEMBER 2003
DSC-5907/17
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IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
This device includes a Retransmit from Mark feature that utilizes two control
inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect
to the RCLK, the memory location being read at that point will be marked. Any
subsequent retransmit operation, RTgoes LOW, will reset the read pointer to
this ‘marked’ location.
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x36/x18) and read
out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
be read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the long word written into the
FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
is configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 5 for Bus-Matching Byte Arrangement.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip
Select is synchronized to the RCLK. Both the output enable and read chip select
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
The TeraSync FIFO has the capability of operating its ports (write and/or
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input SHSTL is also provided, this allows the user
to select HSTL operation for other pins on the device (not associated with the
write or read ports).
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 are fabricated using IDT’s high speed sub-
micron CMOS technology.
5
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| Information | Total 57 Pages | |
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| Download | [ IDT72T3685.PDF Datasheet ] | |
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