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PDF AD5532B Data sheet ( Hoja de datos )
| Número de pieza | AD5532B | |
| Descripción | 14-Bit DAC | |
| Fabricantes | Analog Devices | |
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a
32-Channel, 14-Bit DAC with Precision
Infinite Sample-and-Hold Mode
AD5532B*
FEATURES
High Integration:
32-Channel DAC in 12 mm ؋ 12 mm CSPBGA
Guaranteed Monotonic to 14 Bits
Infinite Sample-and-Hold Capability to ؎0.018% Accuracy
Infinite Sample-and-Hold Total Unadjusted Error ؎2.5 mV
Adjustable Voltage Output Range
Readback Capability
DSP/Microcontroller Compatible Serial Interface
Output Impedance 0.5 ⍀
Output Voltage Span 10 V
Temperature Range –40؇C to +85؇C
APPLICATIONS
Automatic Test Equipment
Optical Networks
Level Setting
Instrumentation
Industrial Control Systems
Data Acquisition
Low Cost I/O
GENERAL DESCRIPTION
The AD5532B is a 32-channel, voltage output, 14-bit DAC with
an additional precision infinite sample-and-hold mode. The
selected DAC register is written to via the 3-wire serial inter-
face and VOUT for this DAC is then updated to reflect the new
contents of the DAC register. DAC selection is accomplished via
address bits A0–A4. The output voltage range is determined by
the offset voltage at the OFFS_IN pin and the gain of the
output amplifier. It is restricted to a range from VSS + 2 V to
VDD – 2 V because of the headroom of the output amplifier.
The device is operated with AVCC = +5 V ± 5%, DVCC = +2.7 V
to +5.25 V, VSS = –4.75 V to –16.5 V, and VDD = +8 V to +16.5 V
and requires a stable 3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1. 32-channel, 14-bit DAC in one package, guaranteed
monotonic.
2. The AD5532B is available in a 74-lead CSPBGA with a body
size of 12 mm ϫ 12 mm.
3. In infinite sample-and-hold mode, a total unadjusted error of
± 2.5 mV is achieved by laser-trimming on-chip resistors.
FUNCTIONAL BLOCK DIAGRAM
DVCC AVCC
REF IN REF OUT OFFS IN
VDD VSS
AD5532B
VIN
TRACK / RESET
BUSY
DAC GND
AGND
DGND
SER /PAR
ADC
MUX
DAC
14-BIT
BUS
DAC
MODE
INTERFACE
CONTROL
LOGIC
DAC
ADDRESS INPUT REGISTER
SCLK DIN DOUT
SYNC / CS A4–A0 CAL OFFSET_SEL
VOUT 0
VOUT 31
OFFS OUT
WR
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
PARALLEL INTERFACE TIMING DIAGRAM
CS
WR
A4–A0, CAL,
OFFS SEL
Figure 1. Parallel Write (ISHA Mode Only)
AD5532B
200A
IOL
TO
OUTPUT
PIN
CL
50pF
200A
IOH
1.6V
Figure 2. Load Circuit for DOUT Timing Specifications
SERIAL INTERFACE TIMING DIAGRAMS
SCLK
SYNC
DIN
t1
1 2 34 5 6 7 8 9
t3 t2
t4 t5
t6
MSB
Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes)
10
LSB
SCLK
SYNC
DIN
t1
12 34 5
t3 t2
21 22 23 24
t4
MSB
t5
t6
Figure 4. 24-Bit Write (DAC Mode)
t11
LSB
1
SCLK 10
SYNC
DOUT
t7 t1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
t12 t2
t10 t4
t8
t9
MSB
Figure 5. 14-Bit Read (Both Readback Modes)
LSB
REV. A
–5–
5 Page 
AD5532B
FUNCTIONAL DESCRIPTION
The AD5532B can be thought of as consisting of 32 DACs and
an ADC (for ISHA mode) in a single package. In DAC mode,
a 14-bit digital word is loaded into one of the 32 DAC registers
via the serial interface. This is then converted (with gain and
offset) into an analog output voltage (VOUT0–VOUT31).
To update a DAC’s output voltage, the required DAC is addressed
via the serial port. When the DAC address and code have been
loaded, the selected DAC converts the code.
On power-on, all the DACs, including the offset channel, are
loaded with zeros. Each of the 33 DACs is offset internally by
50 mV (typ) from GND so the outputs VOUT0 to VOUT31 are
50 mV (typ) on power-on if the OFFS_IN pin is driven directly by
the on-board offset channel (OFFS_OUT), i.e., if OFFS_IN =
OFFS_OUT = 50 mV = > VOUT = (Gain × VDAC) – (Gain –1) ×
VOFFS_IN = 50 mV.
Output Buffer Stage—Gain and Offset
The function of the output buffer stage is to translate the 50 mV–3 V
typical output of the DAC to a wider range. This is done by
gaining up the DAC output by 3.52 and offsetting the voltage
by the voltage on OFFS_IN pin.
VOUT = 3.52 × VDAC – 2.52 × VOFFS _ IN
VDAC is the output of the DAC.
VOFFS_IN is the voltage at the OFFS_IN pin.
Table I shows how the output range on VOUT relates to the offset
voltage supplied by the user:
Table I. Sample Output Voltage Ranges
VOFFS_IN
(V)
0
1
2.130
VDAC (Typ)
(V)
0.05 to 3
0.05 to 3
0.05 to 3
VOUT (Typ)
(V)
0.176 to 10.56
–2.34 to +8.04
–5.192 to +5.192
VOUT is limited only by the headroom of the output amplifiers.
VOUT must be within maximum ratings.
Offset Voltage Channel
The offset voltage can be externally supplied by the user at
OFFS_IN or it can be supplied by an additional offset voltage
channel on the device itself. The offset can be set up in two ways.
In ISHA mode the required offset voltage is set up on VIN
and acquired by the offset channel. In DAC mode, the code
corresponding to the offset value is loaded directly into the
offset DAC. This offset channel’s DAC output is directly
connected to the OFFS_OUT pin. By connecting OFFS_OUT to
OFFS_IN this offset voltage can be used as the offset voltage
for the 32 output amplifiers. The offset must be chosen so
that VOUT is within maximum ratings.
Reset Function
The reset function on the AD5532B can be used to reset all nodes
on this device to their power-on-reset condition. This is imple-
mented by applying a low going pulse of between 90 ns and 200 ns
to the TRACK/RESET pin on the device. If the applied pulse is
less than 90 ns, it is assumed to be a glitch and no operation
takes place. If the applied pulse is wider than 200 ns, this pin
adopts its track function on the selected channel, VIN is switched
to the output buffer, and an acquisition on the channel will not
occur until a rising edge of TRACK.
ISHA Mode
In ISHA mode the input voltage VIN is sampled and converted
into a digital word. The noninverting input to the output buffer
(gain and offset stage) is tied to VIN during the acquisition period
to avoid spurious outputs while the DAC acquires the correct
code. This is completed in 16 µs max. At this time, the updated
DAC output assumes control of the output voltage. The output
voltage of the DAC is connected to the noninverting input of
the output buffer. Since the channel output voltage is effectively
the output of a DAC, there is no droop associated with it. As
long as power is maintained to the device, the output voltage
will remain constant until this channel is addressed again. Since
the internal DACs are offset by 70 mV (max) from GND, the
minimum VIN in ISHA mode is 70 mV. The maximum VIN is
2.96 V due to the upper dead band of 40 mV (max).
Analog Input (ISHA Mode)
The equivalent analog input circuit is shown in Figure 8. The
capacitor C1 is typically 20 pF and can be attributed to pin
capacitance and 32 off-channels. When a channel is selected, an
extra 7.5 pF (typ) is switched in. This capacitor C2 is charged
to the previously acquired voltage on that particular channel
so it must charge/discharge to the new level. It is essential that the
external source can charge/discharge this additional capacitance
within 1 µs to 2 µs of channel selection so that VIN can be
acquired accurately. For this reason a low impedance source
is recommended.
ADDRESSED
CHANNEL
VIN
C1
20pF
C2
7.5pF
Figure 8. Analog Input Circuit
Large source impedances will significantly affect the performance
of the ADC. This may necessitate the use of an input buffer
amplifier.
TRACK Function (ISHA Mode)
Normally in ISHA mode of operation, TRACK is held high and
the channel begins to acquire when it is addressed. However, if
TRACK is low when the channel is addressed, VIN is switched to
the output buffer and an acquisition on the channel will not
occur until a rising edge of TRACK. At this stage the BUSY pin
will go low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and
VIN is free to change again without affecting this output value.
This is useful in an application where the user wants to ramp up
VIN until VOUT reaches a particular level (Figure 9). VIN does
not need to be acquired continuously while it is ramping up.
TRACK can be kept low and only when VOUT has reached its
desired voltage is TRACK brought high. At this stage, the
acquisition of VIN begins.
In the example shown, a desired voltage is required on the output
of the pin driver. This voltage is represented by one input to a
comparator. The microcontroller/microprocessor ramps up the
input voltage on VIN through a DAC. TRACK is kept low
while the voltage on VIN ramps up so that VIN is not continu-
ally acquired. When the desired voltage is reached on the output
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD5532B.PDF ] | |
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