PDF AD9910 Data sheet ( Hoja de datos )

Número de pieza	AD9910
Descripción	3.3V CMOS Direct Digital Synthesizer
Fabricantes	Analog Devices
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Data Sheet 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer AD9910 FEATURES 1 GSPS internal clock speed (up to 400 MHz analog output) Integrated 1 GSPS, 14-bit DAC 0.23 Hz or better frequency resolution Phase noise ≤ −125 dBc/Hz @ 1 kHz offset (400 MHz carrier) Excellent dynamic performance with >80 dB narrow-band SFDR Serial input/output (I/O) control Automatic linear or arbitrary frequency, phase, and amplitude sweep capability 8 frequency and phase offset profiles Sin(x)/(x) correction (inverse sinc filter) 1.8 V and 3.3 V power supplies Software and hardware controlled power-down 100-lead TQFP_EP package Integrated 1024 word × 32-bit RAM PLL REFCLK multiplier Parallel datapath interface Internal oscillator can be driven by a single crystal Phase modulation capability Amplitude modulation capability Multichip synchronization APPLICATIONS Agile local oscillator (LO) frequency synthesis Programmable clock generators FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers Polar modulators Fast frequency hopping FUNCTIONAL BLOCK DIAGRAM AD9910 HIGH SPEED PARALLEL DATA INTERFACE LINEAR RAMP GENERATOR 1024- ELEMENT RAM REFCLK MULTIPLIER 1GSPS DDS CORE 14-BIT DAC TIMING AND CONTROL SERIAL CONTROL DATA PORT Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet REVISION HISTORY 10/2016—Rev. D to Rev. E Change to Figure 33 ........................................................................25 5/2012—Rev. C to Rev. D Changes to Table 1 ............................................................................8 Changes to Table 3 ..........................................................................12 Changes to Figure 39 ......................................................................31 Changes to Synchronization of Multiple Devices Section.........45 Changes to Table 18 ........................................................................55 Changes to Table 20 ........................................................................58 Changes to Table 26 ........................................................................60 8/2010—Rev. B to Rev. C Changes to XTAL_SEL Input Parameter in Table 1 .....................8 Changes to Table 2 ............................................................................9 Changes to Transmit Enable (TxENABLE) Section ...................21 12/2008—Rev. A to Rev. B Changes to Figure 2...........................................................................5 Changes to I/O_UPDATE Pulse Width Parameter and Minimum Profile Toggle Period Parameter in Table 1 ................7 Added XTAL_SEL Input Parameter in Table 1 .............................8 Changes to Table 3 ..........................................................................11 Changes to Figure 20 ......................................................................16 Changes to Figure 22 ......................................................................17 Changes to Figure 23 ......................................................................18 Changes to Figure 24 ......................................................................19 Changes to Figure 25 ......................................................................20 Changes to REF_CLK/REF_CLK Overview Section .................24 Changes to Crystal Driven REF_CLK/REF_CLK Section ........25 Changes to PLL Lock Indication Section and Output Shift Keying (OSK) Section.....................................................................27 Changes to DRG Slope Control Section and Normal Ramp Generation Section..........................................................................30 Changes to Drover Pin Section .....................................................32 Changes to Figure 43 ......................................................................35 Changes to Figure 45 and Internal Profile Control Continuous Waveform Timing Diagram Section.............................................38 Changes to Figure 47 ......................................................................40 AD9910 Changes to Figure 48 ......................................................................41 Deleted I/O_UPDATE Pin Section ..............................................41 Changes to Profiles Section ...........................................................42 Added I/O_UPDATE, SYNC_CLK, and System Clock Relationships Section......................................................................42 Added Figure 49; Renumbered Sequentially...............................42 Changes to Synchronization of Multiple Devices Section.........44 Changes to DVDD (1.8V) (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, and Pin 64) Section and AVDD (1.8V) (Pin 89 and Pin 92) Section.................................................................................47 Changes to Control Interface—Serial I/O Section .....................48 Changes to Table 17 ........................................................................50 Changes to Table 19 ........................................................................57 Changes to Table 20 and Table 21 .................................................58 2/2008—Rev. 0 to Rev. A Changes to Features ..........................................................................1 Changes to REFCLK Multiplier Specification in Table 1 ............5 Changes to Minimum Setup Time to SYNC_CLK.......................6 Changes to I/O Update/Profile[2:0] Timing Characteristics ......6 Changes to TxENABLE/Data Setup Time (to PDCLK) and TxENABLE/Data Hold Time (to PDCLK)....................................6 Changes to Miscellaneous Timing Characteristics.......................6 Changes to Table 3 ..........................................................................10 Changes to Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, and Figure 14 ...................................................................................12 Changes to Figure 30 and Table 7 .................................................24 Changes to Automatic I/O Update Section .................................41 Added Table 16, Renumbered Sequentially.................................41 Changes to Figure 49 to Figure 53 ................................................43 Added Power Supply Partitioning Section ..................................46 Changes to General Serial I/O Operation Section .....................47 Changes to Table 17 ........................................................................49 Changes to Table 19 ........................................................................56 Changes to Table 20 ........................................................................57 Added Table 32 ................................................................................60 5/2007—Revision 0: Initial Version Rev. E \| Page 3 of 64 5 Page Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 PLL_LOOP_FILTER 2 AVDD (1.8V) 3 AGND 4 AGND 5 AVDD (1.8V) 6 SYNC_IN+ 7 SYNC_IN– 8 SYNC_OUT+ 9 SYNC_OUT– 10 DVDD_I/O (3.3V) 11 SYNC_SMP_ERR 12 DGND 13 MASTER_RESET 14 DVDD_I/O (3.3V) 15 DGND 16 DVDD (1.8V) 17 EXT_PWR_DWN 18 PLL_LOCK 19 NC 20 DVDD_I/O (3.3V) 21 DGND 22 DVDD (1.8V) 23 RAM_SWP_OVR 24 D15 25 PIN 1 INDICATOR AD9910 TQFP-100 (E_PAD) TOP VIEW (Not to Scale) NOTES: 1. EXPOSED PAD SHOULD BE SOLDERED TO GROUND. 2. NC = NO CONNECT. Figure 5. Pin Configuration AD9910 75 AVDD (3.3V) 74 AVDD (3.3V) 73 AGND 72 NC 71 I/O_RESET 70 CS 69 SCLK 68 SDO 67 SDIO 66 DVDD_I/O (3.3V) 65 DGND 64 DVDD (1.8V) 63 DRHOLD 62 DRCTL 61 DROVER 60 OSK 59 I/O_UPDATE 58 DGND 57 DVDD (1.8V) 56 DVDD_I/O (3.3V) 55 SYNC_CLK 54 PROFILE0 53 PROFILE1 52 PROFILE2 51 DGND Rev. E \| Page 9 of 64 11 Page

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